SPRSP54 April 2020 DRA80M
ADVANCE INFORMATION for pre-production products; subject to change without notice.
请参考 PDF 数据表获取器件具体的封装图。
The MCU_ARMSS is a dual-core implementation of the Arm Cortex-R5F processor configured for split/lock operation. It also includes accompanying memories (L1 caches and tightly-coupled memories), standard Arm® CoreSight™ debug and trace architecture, integrated Vectored Interrupt Manager (VIM), ECC Aggregators, and various other modules for protocol conversion and address translation for easy integration into the SoC.
For more information, see MCU Arm Cortex-R5F Subsystem section in the device TRM.