ZHCSA88G August   2012  – August 2021 DLPR410

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Supply Voltage Requirements for Power-On Reset and Power-Down
    7. 6.7 Timing Requirements
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Data Interface
        1. 7.3.1.1 Data Outputs
        2. 7.3.1.2 Configuration Clock Input
        3. 7.3.1.3 Output Enable and Reset
        4. 7.3.1.4 Chip Enable
        5. 7.3.1.5 Configuration Pulse
        6. 7.3.1.6 Revision Selection
    4. 7.4 Device Functional Modes
      1.     
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Component Placement
      2. 10.1.2 Impedance Requirements
      3. 10.1.3 PCB Signal Routing
      4. 10.1.4 Fiducials
      5. 10.1.5 PCB Decoupling Guidelines
        1. 10.1.5.1 Bulk Decoupling
          1. 10.1.5.1.1 DLPR410 Decoupling Capacitors
      6. 10.1.6 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Compatibility
      2. 11.1.2 Device Nomenclature
      3. 11.1.3 Device Markings
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 接收文档更新通知
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 术语表
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Supply Voltage Requirements for Power-On Reset and Power-Down

(see (1))
MINMAXUNIT
tVCCVCCINT rise time from 0 V to nominal voltage (2)0.250ms
VCCPORPOR threshold for VCCINT supply0.5V
tOEROE/ RESET release delay following POR (3)0.530ms
VCCPDPower-down threshold for VCCINT supply0.5V
tRSTTime required to trigger a device reset when the VCCINT supply drops below the maximum VCCPD threshold10ms
VCCINT, VCCO, and VCCJ supplies can be applied in any order.
At power-up, the device requires the VCCINT power supply to monotonically rise to the nominal operating voltage within the specified tVCC rise time. If the power supply cannot meet this requirement, then the device might not perform power-on-reset properly. See Platform Flash PROM Power-Up Requirements, in the Xilinx XCF16P (v2.19) Product Specification for more information.
If the VCCINT and VCCO supplies do not reach their respective recommended operating conditions before the OE/ RESET pin is released, then the configuration data from the PROM is not available at the recommended threshold levels. The configuration sequence must be delayed until both VCCINT and VCCO have reached their recommended operating conditions.