Decoupling capacitors (0.1 µF recommended) are placed to minimize the distance from the decoupling capacitor to the supply and ground pins of the component. It is recommended that the placement of and routing for the decoupling capacitors meet the following guidelines:

• The supply voltage pin of the capacitor must be located close to the device supply voltage pin(s). The decoupling capacitor must have vias to ground and voltage planes. The device can be connected directly to the decoupling capacitor (no via) if the trace length is less than 0.1 inch. Otherwise, the component must be tied to the voltage or ground plane through separate vias.
• The trace lengths of the voltage and ground connections for decoupling capacitors and components must be less than 0.1 inch to minimize inductance.
• The trace width of the power and ground connection to decoupling capacitors and components must be as wide as possible to minimize inductance.
• Connecting decoupling capacitors to ground and power planes through multiple vias can reduce inductance and improve noise performance. Via sharing between components (discreet or integrated) is discouraged.
• Decoupling performance can be improved by utilizing low ESR and low ESL capacitors.