ZHCSE90A September   2015  – October 2015 DLPC910

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input LVDS Interface
      2. 7.3.2  Data Clock
      3. 7.3.3  Data Valid
      4. 7.3.4  Interface Training
      5. 7.3.5  Row and Block Interface
        1. 7.3.5.1 Row Mode
        2. 7.3.5.2 Block Mode
      6. 7.3.6  Control Interface
        1. 7.3.6.1 Complement Data
        2. 7.3.6.2 North South Flip
        3. 7.3.6.3 Watchdog
        4. 7.3.6.4 DMD Power Down
        5. 7.3.6.5 Load4
          1. 7.3.6.5.1 Load4 Row Addressing
          2. 7.3.6.5.2 Load4 Block Clears
      7. 7.3.7  Status Interface
        1. 7.3.7.1 ECP2 Finished
        2. 7.3.7.2 Initialization Active
        3. 7.3.7.3 Reset Active
        4. 7.3.7.4 DMD_IRQ
        5. 7.3.7.5 LED Indicators
          1. 7.3.7.5.1 VLED0
          2. 7.3.7.5.2 VLED1
      8. 7.3.8  Reset and System Clock
        1. 7.3.8.1 Controller Reset
        2. 7.3.8.2 Main Oscillator Clock
      9. 7.3.9  I2C Interface
        1. 7.3.9.1 Configuration Pins
        2. 7.3.9.2 Communications Interface
          1. 7.3.9.2.1 Command Format
      10. 7.3.10 DMD Interface
        1. 7.3.10.1 DDC_DOUT
        2. 7.3.10.2 DDC_SCTRL
        3. 7.3.10.3 DDC_DCLKOUT
        4. 7.3.10.4 DMD Reset Interface
          1. 7.3.10.4.1 Mirror Reset Control
        5. 7.3.10.5 Enable and Interrupt Signals
        6. 7.3.10.6 Serial Control Port
      11. 7.3.11 Flash PROM Interface
        1. 7.3.11.1 JTAG Interface
        2. 7.3.11.2 PGM Interface
    4. 7.4 Device Functional Modes
      1. 7.4.1 DMD Row Operation
        1. 7.4.1.1 Data and Command Write Cycle
      2. 7.4.2 Block Mode Operation
      3. 7.4.3 Block Clear
      4. 7.4.4 Mirror Clocking Pulse
      5. 7.4.5 DMD Array Subset
      6. 7.4.6 Global Mirror Clocking Pulse Consideration
    5. 7.5 Register Map
      1. 7.5.1 Register Table Overview
        1. 7.5.1.1  DESTOP_INTERRUPT Register
        2. 7.5.1.2  MAIN_STATUS Register
        3. 7.5.1.3  DESTOP_CAL Register
        4. 7.5.1.4  DESTOP_DMD_ID_REG Register
        5. 7.5.1.5  DESTOP_CATBITS_REG Register
        6. 7.5.1.6  DESTOP_VERSION Register
        7. 7.5.1.7  DESTOP_RESET_REG Register
        8. 7.5.1.8  DESTOP_INFIFO_STATUS Register
        9. 7.5.1.9  DESTOP_BUS_SWAP Register
        10. 7.5.1.10 DESTOP_DMDCTRL Register
        11. 7.5.1.11 DESTOP_BIT_FLIP Register
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 High Speed Lithography Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. Power Supply Recommendations
    1. 9.1 Power Supply Distribution and Requirements
    2. 9.2 Power Down Sequence
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Design Standards
      2. 10.1.2 Signal Layers
      3. 10.1.3 General PCB Routing
        1. 10.1.3.1 Trace Minimum Spacing
        2. 10.1.3.2 Trace Widths and Lengths
          1. 10.1.3.2.1 LVDS Output Bus Skew
        3. 10.1.3.3 Trace Impedance and Routing Priority
      4. 10.1.4 Power and Ground Planes
      5. 10.1.5 Power Vias
      6. 10.1.6 Decoupling
      7. 10.1.7 Flex Connector Plating
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 器件命名规则
      2. 11.1.2 器件标记
    2. 11.2 文档支持
      1. 11.2.1 相关文档 
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Detailed Description

7.1 Overview

The DLPC910 digital controller provides a reliable high speed data pipe to the DMD, where the digital input on the LVDS interface is configured for the required timing requirements of the DMD. The DMD reflects light by using 1-bit binary encoded patterns, where each mirror is a pixel-to-mirror mapping of the pattern.

7.2 Functional Block Diagram

DLPC910 func_block_dlps064.gif

7.3 Feature Description

7.3.1 Input LVDS Interface

The data input interface consists of four input data buses: DDC_DIN_A, DDC_DIN_B, DDC_DIN_C, and DDC_DIN_D. Each bus contains 16 differential pairs which are synchronous to the rising and falling edges of its associated DDC_DCLK signal.

7.3.2 Data Clock

The data clock interface consists of four differential pairs: DDC_DCLK_A, DDC_DCLK_B, DDC_DCLK_C, and DDC_DCLK_D. Each must operate continuously. All signals associated with the data clock should be synchronous to these signals. For example, DDC_DIN_A and DVALID_A should be synchronous to the rising edge of DDC_DCLK_A. This clock should be valid prior to releasing CTRL_RSTZ. DDC_DCLK is a DDR clock with data loaded on both rising and falling edges of DDC_DCLK. The jitter on this clock is specified in Timing Requirements.

7.3.3 Data Valid

The data valid interface consists of four differential pairs: DVALID_A, DVALID _B, DVALID _C, and DVALID _D. The DVALID signal should be asserted synchronous to the data it is meant to frame. DVALID can be asserted as:

  • Framing individual row loads with breaks between rows, or
  • Framing block loads - for example, the DLP9000XFLS with 16 blocks allows framing 100 contiguous row loads, or
  • Framing the entire DMD load where the DVALID stays active for all DMD row loads with zero invalid data between rows.
If the DVALID frames DMD blocks or the entire DMD, assure that the block and row control signals are adjusted at the proper locations in the data stream. Refer to Block Mode Operation for further information.

7.3.4 Interface Training

The DLPC910 detects the phase differences between the ½ speed clock (used in the device driving the LVDS data) and the internally generated ½ speed data clocks to select a clock phase for data capture. This is done by supplying a simple repeating pattern on all of the data inputs while the INIT_ACTIVE output of the DLPC910 is high/active. The details of the training pattern are described below.

Figure 3 shows a simple block diagram of the training pattern insertion logic.

DLPC910 training_pattern_logic_dlps064.gif Figure 3. Block Diagram of Training Pattern Logic

The expected training pattern is 0100. In Figure 4, the data input to the 4:1 SERDES cells is captured on the rising edge of the ½ speed system clock. The output latency shown is based on the documentation for the Xilinx SERDES cells. Individual implementation may vary depending on the type of cells, technology, and design technique used.

DLPC910 td_11_training_pattern_alignmnt_dlps064.gif Figure 4. Training Pattern Alignment

NOTE

In Xilinx FPGAs (due to the construction of the ISERDES and OSERDES cells) a pattern of 0010 needs to be applied to the output/transmitting SERDES cells data pins (D1 = 0, D2 = 0, D3 = 1, D4 = 0) in order to receive a result of 0100 (Q1 = 0, Q2 = 1, Q3 = 0, Q4 = 0) at the input/receiving SERDES cell.

The patterns should be applied on all of the data and DVALID pins. In this respect, the interface is treated as a 17 bit interface with DVALID being the 17th data bit. The receiving logic in the DLPC910 adjusts the clock phase until the correct pattern is seen at the inputs. This allows DLPC910 to correctly select a clock phase for data capture and will contribute to a more robust interface. It is important that the training pattern is applied to the DVALID and data inputs of the DLPC910 before reset to the device is de-asserted, as training commences immediately on the de-assertion of reset. The INIT_ACTIVE signal is asserted while the device is held in reset in order to help facilitate this behavior.

7.3.5 Row and Block Interface

7.3.5.1 Row Mode

The DMD incorporates single row write operations using a row address counter that is randomly addressable. ROWMD(1:0) determines the single row write count mode and ROWAD(10:0) determines the single row write address. ROWMD and ROWAD must be asserted and de-asserted synchronously with DVALID. Row address orientation depends on the North or South Flip Flag (NS_FLIP) input to the DLPC910. Refer to 相关文档  for the DMD datasheet regarding orientation of rows, columns, and Mirror Clocking Pulse (MCP) blocks. The row address counter does not automatically wrap-around when using the increment row address pointer instruction. After the final row is addressed, the row address pointer must be cleared to 0.

7.3.5.2 Block Mode

The signals RST2BLKZ, BLK_MD and BLK_AD are used to designate which mirror block(s) is to be issued a MCP or a Block Clear.

7.3.6 Control Interface

7.3.6.1 Complement Data

By setting the COMP_DATA input high (logic 1), the user is able to command the DMD to internally complement its data inputs prior to loading the data into the mirror array. At least 0.6 ms is needed for the signal to be loaded. This signal should not be used to invert data on a row basis. When used with the Clear command, the mirrors are still set to zero regardless of the COMP_DATA bit. The COMP_DATA signal should be kept low during initialization to ensure proper setup of the system.

7.3.6.2 North South Flip

The NS_FLIP signal allows the user to specify the loading direction of rows in the DMD when used with ROWMD = 01. This control has no effect if ROWMD = 10. Table 1 and Table 2 describe the effect of N/S flip. If NS_FLIP is set, this does not reverse the direction of MCP groups. For example, the normal case is to MCP blocks 0 – 15 in order. When NS_FLIP is set, the order of block MCPs must be reversed to 15 – 0. The NS_FLIP signal should be kept low during initialization to ensure proper setup of the system.

Table 1. Row Write Modes - N/S Flip Flag = 0

ROWMD ROWAD ACTION
1 0 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 None
0 1 0 0 0 0 0 0 0 0 0 0 0 Increment row address pointer and write the concurrent data into that row
1 0 R R R R R R R R R R R Set row address pointer to R and write the concurrent data into that row.
1 1 0 0 0 0 0 0 0 0 0 0 0 Clear row address pointer to 0 and write concurrent data into first row
(that is, row 0).

Table 2. Row Write Modes - N/S Flip Flag = 1

ROWMD ROWAD ACTION
1 0 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 None
0 1 0 0 0 0 0 0 0 0 0 0 0 Decrement the row address pointer and write the concurrent data into that row
1 0 R R R R R R R R R R R Set the row address pointer to R and write the concurrent data into that row.
1 1 0 0 0 0 0 0 0 0 0 0 0 Set row address pointer to row = last row and write concurrent data into last row
(that is, the last row = 1599).

7.3.6.3 Watchdog

The DLPC910 contains a watchdog timer that initiates a global DMD MCP in the event that any DMD reset block has not received a MCP within 10 seconds. This auto-MCP function can be disabled by asserting WDT_ENBLZ high. Disabling the watchdog is not recommended unless the user ensures that a MCP to the entire DMD occurs within 10 seconds. During the time when the DLPC910 is in idle mode or is not operating, it is recommended to exercise the DMD mirrors by continuously loading alternating all-on/all-off patterns.

7.3.6.4 DMD Power Down

For correct power down operation of the DMD, the following power down procedure must be executed.

Prior to power removal, assert PWR_FLOAT and allow approximately 300 μs for the procedure to complete. This procedure will assure the mirrors are in a flat state. Following this procedure, the power can be safely removed. To restart after assertion of PWR_FLOAT, the DLPC910 must be reset by setting CTRL_RSTZ low (logic 0) for 50ms, and then back to high (logic 1), or power to the DLPC910 must be cycled.

To avoid leaving a static image on the DMD without removing power, a mirror FLOAT operation can be issued to the DMD. A mirror FLOAT sequence begins by asserting the proper BLK_MD and BLK_AD as described in Table 5. During the following row cycle, the DMD releases the tension under each mirror so that all mirrors are in a relatively flat position. The FLOAT operation takes approximately 300 μs to complete, during which time RST_ACTIVE is asserted. Normal operation may then continue without reseting or cycling power to the DLPC910 or the DMD.

7.3.6.5 Load4

Load4 functionality provides improved global binary pattern rates for applications that can trade diminished vertical resolution for higher pattern rates. Examples of these types of applications are shutter or chopper applications and vertical structured light patterns. Asserting LOAD4_ENZ causes the attached DMD to load 4 rows for every row of data sent, reducing the pattern load time to ¼ of a full DMD load. It does not reduce the MCP timing.

7.3.6.5.1 Load4 Row Addressing

In Load4 mode, automatic increment mode and row address mode can still be used as before, however the largest addressable row will be (1600/4) - 1 = 399. The addressable vertical resolution is reduced by four, although the physical resolution is unchanged.

Automatic increment address mode will automatically increment the row address input by one (or decrement by one for N/S flip). The row address input will be re-mapped as shown in Table 3, where Vres = the vertical resolution of the DMD.

Table 3. Load4 Row Address Mapping

ROW ADDRESS INPUT PHYSICAL ROWS LOADED ON DMD
0 0, 1, 2, 3
1 4, 5, 6, 7
2 8, 9, 10, 11
3 12, 13, 14, 15
N 4N, 4N+1, 4N+2, 4N+3
(VRes/4) -1 VRes-4, VRes-3, VRes-2, VRes-1
DLPC910 load_4_row_add_DLPS064.gif Figure 5. Example Load4 Row Address Mapping

7.3.6.5.2 Load4 Block Clears

While Load4 is enabled, Block Clear requests will be ignored. To load using Load4 followed by Block Clear request(s), simply de-assert LOAD4_ENZ at the beginning of the MCP request(s) preceding the Block Clear request(s). Re-assert LOAD4_ENZ at the beginning of the MCP request(s) preceding the next desired Load4 operation. This will ensure that the DLPC910 controller has sufficient time to disable or enable LOAD4_ENZ before data is loaded or Block Clear(s) are requested. Refer to Block Clear regarding block clear operation.

7.3.7 Status Interface

7.3.7.1 ECP2 Finished

When power is applied, the ECP2_FINISHED signal goes high to indicate the DLPC910 has completed loading the configuration from the DLPR910 prom.

7.3.7.2 Initialization Active

The initialization active signal INIT_ACTIVE indicates that the DMD and the DLPC910 digital controller are in an initialization state after power is applied. During this initialization period, the DLPC910 is calibrating the data interface, and initializing the DMD by setting all internal registers to their correct states. Monitoring the INIT_ACTIVE signal should not begin until ECP2_FINISHED goes high. When this signal goes low, the system has completed initialization. System initialization takes approximately 4 ms to complete. Data and command write cycles must not be asserted during the initialization. This signal is driven by a CLK_R register and should be considered an asynchronous signal. Standard synchronization techniques should be applied if monitoring this signal with a synchronous circuit clocked by a clock other than CLK_R. After initialization is complete, a delay of at least 64 clocks should be observed before the first DVALID is asserted (to ensure a clean start up process).

NOTE

The RST2BLKZ, COMP_DATA, and NS_FLIP signals should be kept low during initialization to ensure proper setup of the system.

7.3.7.3 Reset Active

The reset active signal RST_ACTIVE goes high for approximately 4 µs, indicating a MCP operation is in progress. During this time, no additional MCPs will be accepted by the DLPC910 until RST_ACTIVE returns low. RST_ACTIVE does not return to low unless continuous no-op or data loading row cycles are issued.

After PWR_FLOAT is asserted, a Mirror Clocking Pulse is issued, or a mirror Float operation is requested, RST_ACTIVE is asserted to indicate that the operation is in progress. Each RST_ACTIVE pulse applies to one or more MCPs depending on the reset block operation chosen from Table 5. RST_ACTIVE is synchronized to an internal version of DDC_DCLK. As such, circuits in the application FPGA should consider this signal asynchronous and use standard synchronization techniques to assure reliable registering of this signal.

7.3.7.4 DMD_IRQ

The DMD_IRQ signal indicates a DMD power fault of one of the bias, offset, or reset power supplies. If the customer interface wishes to monitor this signal, it must first be enabled in the DESTOP_INTERRUPT Register. The cause of the fault should be determined and resolved prior to a system reset to continue operation. The customer interface can also monitor this event by polling the DESTOP_INTERRUPT Register via the I2C interface.

7.3.7.5 LED Indicators

7.3.7.5.1 VLED0

The VLED0 signal is typically connected to an LED to show that the DLPC910 is operating normally. The signal is 1 Hz with 50% duty cycle, otherwise known as the heartbeat.

7.3.7.5.2 VLED1

The VLED1 signal is typically connected to an LED indicator to show the status of system initialization and the status of the clock circuits. The VLED1 signal is asserted only when system initialization is complete and clock circuits are initialized. Logically, these signals are ANDed together to show an indication of the health of the system. If the Phase Locked Loop (PLL) connected to the data clock and the DMD clock are functioning correctly after system initialization, the LED will be illuminated.

7.3.8 Reset and System Clock

7.3.8.1 Controller Reset

The controller reset input CTRL_RSTZ is an active low, asynchronous reset. This reset can be sourced from a voltage supervisor or from the customer interface. Users should note that the chipset will not operate correctly if all DLPC910 power supplies are not in range at the time this reset is released.

7.3.8.2 Main Oscillator Clock

The reference clock, CLKIN_R, supplied from an oscillator must be 50MHz. This is required for the precise timing used to perform the DMD MCP. This clock should be valid prior to releasing CTRL_RSTZ.

7.3.9 I2C Interface

The I2C interface is compliant to I2C specification version 1.0 – 1995, and operates between 100 kHz and 400 kHz clock rate. The interface allows the user to set controller configuration and provides status information such as:

  • Controller and DMD identification
  • DMD Type
  • Versions
  • Controller operating status
  • Controller operating modes
Each I2C clock and data I/O requires an external 1K-Ω pull-up resistor to 3.3 V. Depending on the speed that is selected and the loading of the interface, a different pull-up resistor may be required.

7.3.9.1 Configuration Pins

The DDC_IIC_ADDR_SEL input signal allows the user to select the DLPC910 I2C slave address. When this pin is low, the slave address is 0x34 and when high the slave address is 0x36. If pin is left unconnected, the default slave address is 0x36.

The DDC_IIC_SCL is the master controller input clock. The DDC_IIC_SDA is the bidirectional data signal. Both these signals require a 1-kΩ pull-up resistor.

7.3.9.2 Communications Interface

Communications is performed over the I2C interface where the DLPC910 is the slave device. The DLPC910 slave address consists of a 7-bit address plus 1 R/W bit. Communicating with the DLPC910 involves writing to or reading from the registers listed in Register Map.

7.3.9.2.1 Command Format

All register addresses are 32-bit in size, where each register contains a 32-bit value. The actual valid bits are shown in each respective register. Most registers contain spare or unused bits. These bits should be treated as don't-care during a read operation unless otherwise specified. When writing to spare or unused bits, these bits MUST be set to 0. Both the register address and the data require the least-significant byte to be first and most-significant byte last. A SUB CMD must precede the register address to indicate the type of operation, where a 0xF1 indicates a write operation and a 0xF2 indicates a read operation. The following figures show examples of writing and reading to the DESTOP_BUS_SWAP register.

Figure 6 shows an I2C master writing data to the DLPC910, where 0xF1 is required as the SUB CMD followed by the register address and finally the register data.

DLPC910 master_transmit_lps065.gif Figure 6. Example I2C Master Writing DLPC910 Register Data

Figure 7 shows an I2C master reading data from the DLPC910, where 0xF2 is required as the SUB CMD followed by the register address. Then the master performs STOP followed by a START to read the register data.

DLPC910 master_read_lps065.gif Figure 7. Example I2C Master Reading DLPC910 Register Data

7.3.10 DMD Interface

7.3.10.1 DDC_DOUT

The controller provides four (A, B, C, D) 16-bit wide 2x LVDS output data buses to the DMD with a user selectable bus frequency of 400 or 480 Mhz.

7.3.10.2 DDC_SCTRL

The controller provides four (A, B, C, D) control output buses to the DMD. Each bus provides the necessary control data for the different operating modes of the DMD.

7.3.10.3 DDC_DCLKOUT

The controller provides four (A, B, C, D) clock outputs to the DMD with a clock frequency of 400 or 480 Mhz (user selectable). Both DDC_DOUT and DDC_SCTRL are clocked into the DMD on both the rising and falling edges of the DDC_DCLKOUT.

7.3.10.4 DMD Reset Interface

7.3.10.4.1 Mirror Reset Control

The controller provides the necessary mirror reset control signals to the DMD, which are:

  • RESET_ADDR(3:0) – Reset Driver Address Select.
  • RESET_MODE(3:0) – Reset Driver Mode Select.
  • RESET_SEL(1:0) – Reset Driver Level Select.
  • RESET_STRB – Reset Address, Mode, and Level Select latched on rising-edge.

7.3.10.5 Enable and Interrupt Signals

The controller provides the necessary outputs for DMD enables and an input interrupt from the DMD, which are:

  • PWRDNZ – Active-low DMD reset.
  • RESET_OEZ – Active-low output enable for the DMD reset driver circuits.
  • RESETZ – Active-low sets the reset circuits in known state.
  • RESET_IRQZ – Active-low input interrupt from the DMD.

7.3.10.6 Serial Control Port

The DLPC910 communicates with the DMD over the SCP bus to perform initialization, set configuration, and retrieve identification information.

7.3.11 Flash PROM Interface

7.3.11.1 JTAG Interface

The JTAG interface has multiple purposes that can be used in the following manner:

  • Program the configuration bit stream directly into the DLPC910
  • Perform boundary test and debug of the DLPC910
  • Program the configuration bit stream directly into the DLPR910YVA PROM (not user configurable)

7.3.11.2 PGM Interface

The PGM(4:0) interface is used by the DLPC910 to read in the configuration bit stream from the attached DLPR910YVA PROM.

7.4 Device Functional Modes

7.4.1 DMD Row Operation

The DMD data is loaded one row at a time with four LVDS buses into the DMD SRAM pixels. The DMD requires all four data buses (A,B,C,D). Each bus consists of a differential clock (DDC_DCLKOUT), a differential control signal (DDC_SCTRL), and 16 differential pairs of LVDS signals (DDC_DOUT[15:0]) that are output from the DLPC910. Data and control are clocked into the DMD on both the rising and falling edges of the DDC_DCLKOUT_[A, B, C, D]. Data loading does not cause mirror switching until a MCP operation is completed.

The number of clocks to load a row can be calculated as:

Equation 1. C = P / (D × E)

where

  • C = number of clocks per row
  • P = number of pixels per row
  • D = data bus bit width
  • E = 2. (Data is clocked on both the rising an falling edge of DCLK.)

Example:
C = 2560 / (64 × 2) = 20 clocks per row

Row address orientation depends on the North or South Flip Flag (NS_FLIP) input to the DLPC910. Refer to 相关文档  for the DMD datasheet regarding orientation of rows, columns, and MCP blocks. The row address counter does not automatically wrap-around when using the increment row address pointer instruction. After the final row is addressed, the row address pointer must be cleared to 0.

7.4.1.1 Data and Command Write Cycle

Once initialization is complete (INIT_ACTIVE = 0) the user is free to send data and control information to the DLPC910. When the user asserts the DVALID signal for the LVDS input buses, the DLPC910 begins sampling the LVDS data inputs and synchronously sending this information to the DMD along with row address control information. The row cycle period is exactly 20 CLKS long and begins with DVALID. If DVALID is removed, the DLPC910 stops loading data and control information until DVALID goes active again.

Figure 8 shows an example of data written to the DLPC910 for a single row. Data is written to the DMD 64 bits (16 A bits + 16 B bits + 16 C bits + 16 D bits) on each clock edge. An entire line must be written for data to be latched into memory.

The DMD incorporates single row write operations using a row address counter that is randomly addressable. As shown in Table 1 and Table 2, ROWMD(1:0) determines the single row write count mode and ROWAD(10:0) determines the single row write address. ROWMD and ROWAD must be asserted and de-asserted synchronously with DVALID and must be valid synchronous to the beginning of the data as shown in Figure 8.

DLPC910 td_03_sngl_row_write_oper_dlps064.gif Figure 8. Single Row Write Operation

7.4.2 Block Mode Operation

The DMD mirrors and corresponding SRAM pixels are organized into blocks and each block is broken into rows per BLK as described in Table 4. Mirror blocks are addressed for either the Mirror Clocking Pulse or Block Clear functions by asserting block control signals at the start of each row data load. RST2BLKZ, BLK_MD and BLK_AD are used as shown in Table 5 to designate which mirror block(s) is to be issued a MCP or a Block Clear. Refer to 相关文档  for the DMD datasheet regarding block location information.

  • The clear operation sets all of the SRAM pixels in the designated block to logic zero during the current row cycle.
  • It is possible to issue a MCP to a block while loading a different block.
  • It is not possible to clear a block while writing to a different block.
  • It is not necessary to clear a block if it is going to be reloaded with new data (just like a normal memory cell).
  • It is recommended that RST2BLKZ, COMP, and NS_FLIP be set to one value and not adjusted during normal system operation.
  • A change in RST2BLKZ is not immediately effective and will require more than one row load cycle to complete.

NOTE

RST2BLKZ, COMP_DATA, and NS_FLIP need to be kept low during initialization for proper setup of the system.

Table 4. Example DMD Characteristics

TYPE DMD_TYPE COLS ROWS BLKS ROWS PER BLK CLKS PER ROW #DATA IN
DLP9000XFLS - 0.9 WQXGA Type A 0×F 2560 1600 16 100 20 64

Table 5. Block Operations

RST2BKLZ BLK_MD 1 BLK_MD 2 BLK_AD 3 BLK_AD 2 BLK_AD 1 BLK_AD 0 OPERATION
X 0 0 X X X X None
X 0 1 0 0 0 0 Clear block 00
X 0 1 0 0 0 1 Clear block 01
X 0 1 0 0 1 0 Clear block 02
X 0 1 0 0 1 1 Clear block 03
X 0 1 0 1 0 0 Clear block 04
X 0 1 0 1 0 1 Clear block 05
X 0 1 0 1 1 0 Clear block 06
X 0 1 0 1 1 1 Clear block 07
X 0 1 1 0 0 0 Clear block 08
X 0 1 1 0 0 1 Clear block 09
X 0 1 1 0 1 0 Clear block 10
X 0 1 1 0 1 1 Clear block 11
X 0 1 1 1 0 0 Clear block 12
X 0 1 1 1 0 1 Clear block 13
X 0 1 1 1 1 0 Clear block 14
X 0 1 1 1 1 1 Clear block 15
X 1 0 0 0 0 0 Reset block 00
X 1 0 0 0 0 1 Reset block 01
X 1 0 0 0 1 0 Reset block 02
X 1 0 0 0 1 1 Reset block 03
X 1 0 0 1 0 0 Reset block 04
X 1 0 0 1 0 1 Reset block 05
X 1 0 0 1 1 0 Reset block 06
X 1 0 0 1 1 1 Reset block 07
X 1 0 1 0 0 0 Reset block 08
X 1 0 1 0 0 1 Reset block 09
X 1 0 1 0 1 0 Reset block 10
X 1 0 1 0 1 1 Reset block 11
X 1 0 1 1 0 0 Reset block 12
X 1 0 1 1 0 1 Reset block 13
X 1 0 1 1 1 0 Reset block 14
X 1 0 1 1 1 1 Reset block 15
0 1 1 0 0 0 0 Reset blocks 00-01
0 1 1 0 0 0 1 Reset blocks 02-03
0 1 1 0 0 1 0 Reset blocks 04-05
0 1 1 0 0 1 1 Reset blocks 06-07
0 1 1 0 1 0 0 Reset blocks 08-09
0 1 1 0 1 0 1 Reset blocks 10-11
0 1 1 0 1 1 0 Reset blocks 12-13
0 1 1 0 1 1 1 Reset blocks 14-15
1 1 1 0 0 0 X Reset blocks 00-03
1 1 1 0 0 1 X Reset blocks 04-07
1 1 1 0 1 0 X Reset blocks 08-11
1 1 1 0 1 1 X Reset blocks 12-15
X 1 1 1 0 X X Reset blocks 00-15
X 1 1 1 1 X X Float blocks 00-15

7.4.3 Block Clear

The DMD incorporates block clear operations using the BLK_MD and BLK_AD signals as shown in Table 5. The block address does not automatically increment and must be set to the desired block to be cleared. Block clear operation writes logic zero data to all the SRAM cells in one DMD block regardless of the COMP_DATA input state. It is not possible to clear a DMD block while writing to a different block. BLK_MD and BLK_AD are asserted to perform a MCP on the block(s) that have been cleared. The customer interface should introduces a delay on the last block(s) that were issued a MCP to allow the mirrors to become stable.Each Block Clear operation must be followed by two no-op row load cycles. Therefore, 16 total Block Clear commands and 32 total no-op row cycles are required to clear the entire DMD array.

7.4.4 Mirror Clocking Pulse

A Mirror Clocking Pulse (MCP) sequence begins by asserting BLK_MD and BLK_AD for a single, dual, quad, or global block operation as defined in Table 5. A MCP causes a reset on the block(s), and the data stored in the block(s) takes effect on the mirrors of the DMD. Shortly after a MCP has been issued, RST_ACTIVE goes high for approximately 4 μs, indicating a MCP operation is in progress. During this time, no additional MCPs may be initiated until RST_ACTIVE returns low. RST_ACTIVE does not return to low unless continuous no-op or data loading row cycles are issued. A typical single block load phased sequence in which consecutive DMD blocks are loaded is illustrated in Figure 10. A MCP time is identical for single, dual, quad or global block operations.

Note that it may take longer to complete a MCP on a block than it does to load a block. The block load time may be calculated as:

Block Load Time = Clock Period × number CLKS per ROW × number ROWS per BLK

Table 6. DMD Block Load Time at 480 MHz DMD Clock

DMD MINIMUM BLOCK LOAD TIME
DLP9000XFLS 4.167 µsec

For any case which involves sending a MCP or a Block Clear without data loading, the customer interface must send no-op row cycles. This can be accomplished by asserting DVALID, while holding ROWMD at 00 and BLKMD at 00 for 20 clock cycles, as in Figure 9. Following the loading of all rows in a block or the entire DMD, at least one no-op row cycle must be completed to initiate the MCP. If the MCP is asserted prior to loading all rows in a block or the entire DMD, rows which were not updated will show old data. Additional MCP operations may not be initiated until RST_ACTIVE is low. Block Clear operations for the DMD must be followed by two consecutive no-op row cycle commands.

To obtain full utilization of the DMD bandwidth, load four blocks and then issue a MCP to the four blocks concurrently by setting RST2BLKZ to 1 and BLK_MD to 11 with the appropriate address in BLK_AD. This is illustrated in Figure 12.

It is possible to load other blocks while the block(s) previously issued a MCP is settling. This is illustrated in Figure 11 and Figure 12, where blocks are reloaded while the mirror setting time is ocurring. It is also possible to load other blocks while previously loaded block(s) have an outstanding RST_ACTIVE. This is illustrated in Figure 12, where block 0 is loaded while RST_ACTIVE is asserted for blocks 12-15.

NOTE

While RST_ACTIVE is high for 4 μs, the data for the block(s) being issued a MCP should not be changed to allow the mirrors to become stable. The RST_ACTIVE does not include the mirror settling period. A short delay of 6 μs should be introduced during the last block(s) that is issued a MCP. The mirror settling time is illustrated in Figure 10, Figure 11, Figure 12, and Figure 13, where the customer interface introduces a delay on the last block(s) that were issued a MCP to allow the mirrors to become stable.

Figure 10, Figure 11, Figure 12, and Figure 13 all show an exposure period. Once the customer interface has issued all required MCPs and the proper mirror settling time has been applied, the customer interface may pulse an illumination source onto the DMD during this period. The exposure period is user adjustable; however, increasing the exposure period decreases the pattern rate. Refer to Application Curves regarding exposure period.

DLPC910 td_06_dmd_no_op_row_cycle_dlps064.gif Figure 9. DMD No-op Row Cycle
DLPC910 Single_Block_Load_Phased_DLPS064.gif Figure 10. Single Block Load Phased Sequence
DLPC910 Dual_Block_Load_Phased_DLPS064.gif Figure 11. Dual Block Load Phased Sequence
DLPC910 Quad_Block_Load_Phase_DLPS064.gif Figure 12. Quad Block Load Phased Sequence
DLPC910 Global_Load_DLPS064.gif Figure 13. Full DMD Global Load Sequence

Note: After a MCP or Block Clear command is given, RST_ACTIVE may not be asserted until up to 60ns (depending on the clock frequency) after the command. While RST_ACTIVE is asserted, no other command should be given.

7.4.5 DMD Array Subset

It is possible to use a subset of the DMD array including individual MCP blocks. The driving software/hardware MUST ensure that the MCP rate for the number of blocks in the subset plus the mirror settling time does not exceed 50 kHz.

Load4 functionality is primarily intended to be used with global MCPs. However, it is possible to use a subset of the DMD array including individual MCP blocks. The driving software/hardware MUST ensure that the MCP rate for the number of blocks in the Load4 subset plus the mirror settling time does not exceed 50 kHz.

7.4.6 Global Mirror Clocking Pulse Consideration

A Global MCP (BLK_MD = 11 and BLK_AD = 10XX), takes the same amount of time as the single, dual, and quad block MCP. In addition to requiring a no-op row cycle to initiate a global MCP, a row cycle (either no-op or data loading) is also required to complete the operation. If the customer interface is monitoring RST_ACTIVE to determine when to send a subsequent row cycle, it will never see RST_ACTIVE transition low. One method of operation would be to continue sending no-op row cycles until RST_ACTIVE goes low then continue loading data with real row cycles. Another method of operation is to delay greater than 10 μs, then start loading new data to DMD.

7.5 Register Map

7.5.1 Register Table Overview

Table 7 lists the I2C accessible memory mapped registers for the DLPC910. Access to the I2C registers should not begin unitl INIT_ACTIVE has transitioned low (logic 0).

Table 7. Communication Registers

ADDRESS REGISTER NAME DESCRIPTION SIZE
0x0000 DESTOP_INTERRUPT DESTOP Interrupt Status 32
0x0004
0x0008
0x000C MAIN_STATUS Main Status 32
0x0010 DESTOP_CAL DESTOP input calibration status 32
0x0014 DESTOP_DMD_ID_REG Connected DMD ID 32
0x0018 DESTOP_CATBITS_REG Connected DMD fuse catalog bits 32
0x001C DESTOP_910VERSION_REG DLPC910 Version Number 32
0x0020 DESTOP_RESET_REG Reset status signals 32
0x0024 DESTOP_INFIFO_STATUS Input interface FIFO status 32
0x0028 DESTOP_BUS_SWAP Output bus swap 32
0x002C DESTOP_DMDCTRL DMD Control Register 32
0x0030 DESTOP_BIT_FLIP Output data bus bit reversal/flip 32

7.5.1.1 DESTOP_INTERRUPT Register

The DESTOP_INTERRUPT register is used for controlling the interrupt source. Interrupts can be enabled, disabled, cleared and read independently.

Table 8. DESTOP_INTERRUPT Register

ADDRESS (1) (2) (3) (4) BITS DESCRIPTION RESET TYPE
0x0000
0x0004
0x0008
0 SPARE 0x0 R/W
1 SPARE 0x0 R
2 A DMD IRQZ event occurred. The only existing source for this event is a DMD power fault indicating bias, offset, or reset power supplies have become inactive. The cause of the fault should be determined and resolved prior to a system reset to continue operation. (5) 0x0 R/W
3 SPARE 0x0 R
31:4 UNUSED 0x0 R
(1) Interrupt status can be obtained by reading 0x0000 or 0x0004 address.
(2) Interrupt bits are asserted either by the corresponding H/W events or by S/W writing a 1 to the target bit of 0x0004 address.
(3) Interrupt bits are cleared by S/W writing a 1 to the target bit in 0x0000 address.
(4) Interrupts are enabled by setting the appropriate bits in register 0x0008.
(5) This bit must be cleared after a power cycle or a reset to the DLPC910.

7.5.1.2 MAIN_STATUS Register

The MAIN_STATUS register is used for reading the status of the DLPC910. The register can be polled during operation to obtain the current state of the DLPC910.

Table 9. MAIN_STATUS Register

ADDRESS BITS DESCRIPTION RESET TYPE
0x000C 0 DMD initialization in progress flag 0x0 R
  0 - No DMD initialization activity
  1 - DMD initialization in progress
1 DMD initialization in progress flag 1 0x0 R
  0 - No DMD stage 1 initialization activity
  1 - DMD stage 1 initialization activity in progress
2 DMD initialization in progress flag 2 0x0 R
  0 - No DMD stage 2 initialization activity
  1 - DMD stage 2 initialization activity in progress
3 DMD supports AB channels 0x0 R
  0 - Operation of DMD AB buses not enabled
  1 - Operation of DMD AB buses enabled
4 DMD supports CD channels 0x0 R
  0 - Operation of DMD CD buses not enabled
  1 - Operation of DMD CD buses enabled
5 Input interface calibration in progress 0x0 R
  0 - Input interface calibration inactive
  1 - Input interface calibration in progress
6 DVALID alignment on interface A ok 0x0 R
  0 - DVALID alignment invalid on channel A
  1 - DVALID alignment correct on channel A
7 DVALID alignment on interface B ok 0x0 R
  0 - DVALID alignment invalid on channel B
  1 - DVALID alignment correct on channel B
8 DVALID alignment on interface C ok 0x0 R
  0 - DVALID alignment invalid on channel C
  1 - DVALID alignment correct on channel C
9 DVALID alignment on interface D ok 0x0 R
  0 - DVALID alignment invalid on channel D
  1 - DVALID alignment correct on channel D
10 System PLL locked flag 0x0 R
  0 - PLL not locked
  1 - PLL locked
11 Reference PLL locked flag 0x0 R
  0 - PLL not locked
  1 - PLL locked
31:12:00 UNUSED 0x0 R

7.5.1.3 DESTOP_CAL Register

The DESTOP_CAL register is used for reading the calibration state of the LVDS input buses of the DLPC910. The calibration occurs during the initialization after power is applied to the DLPC910.

Table 10. DESTOP_CAL Register

ADDRESS BITS DESCRIPTION RESET TYPE
0x0010 0 Input Channel A Calibration complete: 0x0 R
  0 - Channel A Calibration in progress
  1 - Channel A Calibration complete
1 Input Channel B Calibration complete: 0x0 R
  0 - Channel B Calibration in progress
  1 - Channel B Calibration complete
2 Input Channel C Calibration complete: 0x0 R
  0 - Channel C Calibration in progress
  1 - Channel C Calibration complete
3 Input Channel D Calibration complete: 0x0 R
  0 - Channel D Calibration in progress
  1 - Channel D Calibration complete
31:04:00 UNUSED 0x0 R

7.5.1.4 DESTOP_DMD_ID_REG Register

The DESTOP_DMD_ID_REG register is used for reading the identification of the DMD connected to the DLPC910. If the DLPC910 determines the DMD is not supported, the DLPC910 will halt all operations.

Table 11. DESTOP_DMD_ID_REG Register

ADDRESS BITS DESCRIPTION RESET TYPE
0x0014 31:0 Read-only register containing the ID of the connected DMD. 0x0 R

7.5.1.5 DESTOP_CATBITS_REG Register

The DESTOP_CATBITS_REG register is used for reading the remainder of identification of the DMD connected to the DLPC910. If the DLPC910 determines the DMD is not supported, the DLPC910 will halt all operations.

Table 12.

ADDRESS BITS DESCRIPTION RESET TYPE
0x0018 3:0 Read-only register containing the 4 remaining ID bits of the connected DMD. 0x0 R
31:4 UNUSED 0x0 R

7.5.1.6 DESTOP_VERSION Register

The DESTOP_VERSION is used for obtaining the DLPR910 prom configuration program version.

Table 13. DESTOP_VERSION Register

ADDRESS BITS DESCRIPTION
(Read-only register of the DLPC910 version number)
RESET TYPE
0x001C 3:0 Major 0x1 R
7:4 Minor 0x0 R
15:8 Revision 0x0 R
31:16 UNUSED 0x0 R

7.5.1.7 DESTOP_RESET_REG Register

The DESTOP_RESET_REG register is used for reading the current state of the MCP. Reading this register while the DLPC910 is loading data to the DMD may always indicate a “1”. It is best to monitor the actual RST_ACTIVE output signal of the DLPC910 to obtain the real state of the MCP.

Table 14. DESTOP_RESET_REG Register

ADDRESS BITS DESCRIPTION RESET TYPE
0x0020 0 RESET Operation in progress bit: (Mirror clocking pulse)
0 - Reset inactive
1 - Reset active
0x0 R
31:1 UNUSED 0x0 R

7.5.1.8 DESTOP_INFIFO_STATUS Register

The DESTOP_INFIFO_STATUS register is used for validating there is data in the input bus FIFO buffers. An empty FIFO buffer may indicate that the DVALID is not properly set for the data on the input data bus.

Table 15. DESTOP_INFIFO_STATUS Register

ADDRESS BITS DESCRIPTION RESET TYPE
0x0024 0 Channel A input FIFO status:
0 - Channel A FIFO has data
1 - Channel A FIFO is empty
0x0 R
1 Channel B input FIFO status:
0 - Channel B FIFO has data
1 - Channel B FIFO is empty
0x0 R
2 Channel C input FIFO status:
0 - Channel C FIFO has data
1 - Channel C FIFO is empty
0x0 R
3 Channel D input FIFO status:
0 - Channel D FIFO has data
1 - Channel D FIFO Is empty
0x0 R
31:4 UNUSED 0x0 R

7.5.1.9 DESTOP_BUS_SWAP Register

The DESTOP_BUS_SWAP register is used for configuring the DLPC910 output LVDS buses to the DMD. To simplify board layout design, swapping the buses may reduce routing constraints. If the buses are swapped in hardware, then the appropriate setting that matches the hardware must be set after a power cycle or a reset to the DLPC910.

Table 16. DESTOP_BUS_SWAP Register

ADDRESS BITS DESCRIPTION RESET TYPE
0x0028 0 Enables Bus swap for A and B output DMD buses. SCTRLs for A and B output buses are also swapped.
0 = un-swapped (default)
1 = swapped
0x0 R/W
1 Enables Bus swap for C and D output DMD buses. SCTRLs for C and D output buses are also swapped.
0 = un-swapped (default)
1 = swapped
0x0 R/W
31:2 UNUSED 0x0 R

7.5.1.10 DESTOP_DMDCTRL Register

The DESTOP_DMDCTRL register can be used in place of the external DLPC910 control inputs to control the functions described. Bit-0 must be set to “1” to gain control of the functions. Bit-5 is available regardless of the state of bit-0.

Table 17. DESTOP_DMDCTRL Register

ADDRESS BITS DESCRIPTION (1) RESET TYPE
0x002C 0 Enables DMD control of the functions that are normally controlled on external pins. 0x0 R/W
0 = Controlled from external pins (default)
1 = Controlled from the I2C interface
1 NS_FLIP. Sets the orientation of the top and bottom of the DMD. 0x0 R/W
0 = Un-flipped (default)
1 = Flipped
2 DATA_COMP. Sets a DMD mode that inverts all of the incoming data. 0x0 R/W
0 = Normal (default)
1 = Data is inverted at the DMD
3 LOAD_FOUR. Activates the Load4 function of the DMD. Each row written is loaded to 4 consecutive locations. 0x1 R/W
0 = Load4 mode is active
1 = Normal (default)
4 RST2BLKZ. Activates the RST2BLKZ function of the DMD. Refer to Table 5 for setting RST2BLKZ. 0x1 R/W
(1) When bit 0 is set to 1, bits 1, 2, 3, and 4 override their respective external control inputs.

7.5.1.11 DESTOP_BIT_FLIP Register

The DESTOP_BIT_FLIP register is used for configuring the DLPC910 output LVDS buses to the DMD. To simplify board layout design, flipping individual buses may reduce routing constraints. If the buses are flipped in hardware, then the appropriate setting that matches the hardware must be set after a power cycle or a reset to the DLPC910.

Table 18. DESTOP_BIT_FLIP Register

ADDRESS BITS DESCRIPTION RESET TYPE
0x0030 0 Reverses the Data bits for bus A (b'15 = b'0, b'0 = b'15) 0x0 R/W
0 = un-flipped (default)
1 = flipped
1 Reverses the Data bits for bus B (b'15 = b'0, b'0 = b'15) 0x0 R/W
0 = un-flipped (default)
1 = flipped
2 Reverses the Data bits for bus C (b'15 = b'0, b'0 = b'15) 0x0 R/W
0 = un-flipped (default)
1 = flipped
3 Reverses the Data bits for bus D (b'15 = b'0, b'0 = b'15) 0x0 R/W
0 = un-flipped (default)
1 = flipped
31:4 UNUSED 0x0 R