ZHCSE90A September 2015 – October 2015 DLPC910
The DLPC910ZYR, the DLPR910YVA, and the DLP9000XFLS DMD are powered by a power distribution as shown in Figure 16.
Prior to power removal, the Apps FPGA should assert PWR_FLOAT and allow approximately 300 μs for the procedure to complete. This procedure will assure the mirrors are in a flat state. Following this procedure, the power can be safely removed. To restart after assertion of PWR_FLOAT, the DLPC910 must be reset (CTRL_RSTZ low then high) or power must be cycled.