DLPS074 February   2017 DLPC4422

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Configurations and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  System Oscillators Timing Requirements
    7. 6.7  Test and Reset Timing Requirements
    8. 6.8  JTAG Interface: I/O Boundary Scan Application Timing Requirements
    9. 6.9  Port 1 Input Pixel Timing Requirements
    10. 6.10 Port 3 Input Pixel Interface (via GPIO) Timing Requirements
    11. 6.11 DMD LVDS Interface Timing Requirements
    12. 6.12 Synchronous Serial Port (SSP) Interface Timing Requirements
    13. 6.13 Programmable Output Clocks Switching Characteristics
    14. 6.14 Synchronous Serial Port Interface (SSP) Switching Characteristics
    15. 6.15 JTAG Interface: I/O Boundary Scan Application Switching Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 System Reset Operation
        1. 7.3.1.1 Power-up Reset Operation
        2. 7.3.1.2 System Reset Operation
      2. 7.3.2 Spread Spectrum Clock Generator Support
      3. 7.3.3 GPIO Interface
      4. 7.3.4 Source Input Blanking
      5. 7.3.5 Video Graphics Processing Delay
      6. 7.3.6 Program Memory Flash/SRAM Interface
      7. 7.3.7 Calibration and Debug Support
      8. 7.3.8 Board Level Test Support
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Recommended MOSC Crystal Oscillator Configuration
      2. 8.2.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
    1. 9.1 System Power Regulations
    2. 9.2 System Power-Up Sequence
    3. 9.3 Power-On Sense (POSENSE) Support
    4. 9.4 System Environment and Defaults
      1. 9.4.1 DLPC4422 System Power-Up and Reset Default Conditions
      2. 9.4.2 1.1-V System Power
      3. 9.4.3 1.8-V System Power
      4. 9.4.4 3.3-V System Power
      5. 9.4.5 Power Good (PWRGOOD) Support
      6. 9.4.6 5V Tolerant Support
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Layout Guidelines for Internal ASIC Power
      2. 10.1.2 PCB Layout Guidelines for Auto-Lock Performance
      3. 10.1.3 DMD Interface Considerations
      4. 10.1.4 Layout Example
      5. 10.1.5 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Video Timing Parameter Definitions
      2. 11.1.2 Device Nomenclature
      3. 11.1.3 Device Markings
        1. 11.1.3.1 Device Marking
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.3.5 Video Graphics Processing Delay

The DLPC4422 controller introduces a variable number of field/ frame delays dependent on the source type and selected processing steps performed on the source. For optimum audio/ video synchronization this delay must be matched in the audio path. The following tables define various video delay scenarios to aid in audio matching.

Frame and Fields in table refer to source frames and fields.

  • For 2-D sources, “N” is defined to be the ratio of the primary channel source frame rate (or field rate for interlaced video) to the display frame/ field rate.
  • For 3-D sources, “M” is defined to be the ratio of the primary channel source frame rate (or field rate for interlaced video) required to obtain both the left and right image, to the display frame/field rate (The rate at which each eye is displayed).

Table 3. Primary Channel/Video-Graphics Processing Delay

Source 3D Video Decoder De-Interlacing Frame Rate Conversion FRC Type Formatter Buffer Total Delay
50 to 60 Hz Interlaced SDTV Video Disabled Disabled 2 Fields Sync (1:4) M Fields 2 + M Fields
60Hz Progressive Video Disabled Disabled 2 Frames Sync (1:4) M Frames 2 + M Frames
120Hz Progressive Video Disabled Disabled 2 Frames Sync (1:2) M Frames 2 + M Frames
24Hz 1080p Disabled Disabled 1 Frame Sync (1:6) M Frames 1 + M Frames
50 to 60 Hz (720p, 1080p) Disabled Disabled 1 Frame Sync (1:2) M Frames 1 + M Frames
50 to 60 Hz 1080p Disabled Disabled 1 Frame Sync (1:2) M Frames 1 + M Frames
60Hz Interlaced Graphics (VGA-WUXGA) Disabled Disabled 1 Field Sync (1:4) M Frames 1 + M Frames
60 Hz Graphics Disabled Disabled 1 Frame Sync (1:4) M Frames 1 + M Frames
120 Hz Graphics Disabled Disabled 1 Frame Sync (1:2) M Fields 1 + M Fields
50 to 60 Hz Interlaced Disabled Disabled 1 Field Sync(1:2) M Fields 1 + M Fields
50 to 60 Hz Progressive Disabled Disabled 1 Frame Sync(1:2) M Frames 1 + M Frames