ZHCSJA1G April 2010 – January 2019 DLP5500
请参考 PDF 数据表获取器件具体的封装图。
When designing a PCB board for the DLP5500 controlled by the DLPC200 in conjunction with the DLPA200, the following are recommended:
Signal trace corners should be no sharper than 45°. Adjacent signal layers should have the predominate traces routed orthogonal to each other. TI recommends that critical signals be hand routed in the following order: DDR2 Memory, DMD (LVDS signals), then DLPA200 signals.
TI does not recommend signal routing on power or ground planes.
TI does not recommend ground plane slots.
High speed signal traces should not cross over slots in adjacent power and/or ground planes.
DMD_DCKL_xn, and DMD_SCTRL_xn)
|P-to-N data, clock, and SCTRL: <10 mils (0.25 mm); Pair-to-pair <10 mils (0.25 mm); Bundle-to-bundle <2000 mils (50 mm, for example DMD_DAT_Ann to DMD_DAT_Bnn).
All matching should include internal trace lengths. See Pin Configuration and Functions for internal package trace lengths.
Trace width: 4 mil (0.1 mm)
Trace spacing: In ball field – 4 mil (0.11 mm); PCB etch – 14 mil (0.36 mm)
Maximum recommended trace length <6 inches (150 mm)
|Signal Name||Minimum Trace Width||Minimum Trace Spacing||Layout Requirements|
|GND||Maximize||5 mil (0.13 mm)||Maximize trace width to connecting pin as a minimum|
|VCC, VCC2||20 mil (0.51 mm)||10 mil (0.25 mm)|
|MBRST[15:0]||10 mil (0.25 mm)||10 mil (0.25 mm)|