ZHCSHX4B November   2017  – June 2019 DLP3030-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      DLPDLP3030-Q1 系统框图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Configurations and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Physical Characteristics of the Micromirror Array
    11. 6.11 Optical Characteristics of the Micromirror Array
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Micromirror Array
      2. 7.3.2 Double Data Rate (DDR) Interface
      3. 7.3.3 Micromirror Switching Control
      4. 7.3.4 DMD Voltage Supplies
      5. 7.3.5 Logic Reset
      6. 7.3.6 Temperature Sensing Diode
        1. 7.3.6.1 Temperature Sense Diode Theory
      7. 7.3.7 Active Array Temperature
      8. 7.3.8 DMD JTAG Interface
    4. 7.4 Optical Performance
      1. 7.4.1 Numerical Aperture and Stray Light Control
      2. 7.4.2 Pupil Match
      3. 7.4.3 Illumination Overfill and Alignment
    5. 7.5 DMD Image Quality Specification
    6. 7.6 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 HUD Reference Design and LED Controller Reference Design
    3. 8.3 Application Mission Profile Consideration
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Sequencing Requirements
      1. 9.1.1 Power Up and Power Down
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Temperature Diode Pins
    3. 10.3 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 器件命名规则
      2. 11.1.2 器件标记
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 器件处理
    8. 11.8 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.1 Absolute Maximum Ratings

See (1)
MIN MAX UNIT
SUPPLY VOLTAGE
VREF LVCMOS logic supply voltage(2) –0.5 4 V
VCC LVCMOS logic supply voltage(2) –0.5 4 V
VOFFSET Mirror electrode and HVCMOS voltage(2) –0.5 8.75 V
VBIAS Mirror electrode voltage –0.5 17 V
|VBIAS – VOFFSET| Supply voltage delta(3) 8.75 V
VRESET Mirror electrode voltage –11 0.5 V
Input voltage: other Inputs See (2) –0.5 VREF + 0.3 V
fDCLK Clock frequency 60 80 MHz
ITEMP_DIODE Temperature diode current 500 µA
ENVIRONMENTAL
Operating DMD array temperature (TARRAY) (monitored by TMP411-Q1 via DLPC120-Q1) See (4) and Active Array Temperature –40 105 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Unless otherwise indicated, these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to GND (VSS). VBIAS, VCC, VOFFSET, VREF, VRESET, and VSS are required to operate the DMD.
(3) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than or equal to 8.75 V.
(4) Contact TI application engineering for more details about the DMD modeled use profile.