ZHCSHX4B November   2017  – June 2019 DLP3030-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      DLPDLP3030-Q1 系统框图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Configurations and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Physical Characteristics of the Micromirror Array
    11. 6.11 Optical Characteristics of the Micromirror Array
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Micromirror Array
      2. 7.3.2 Double Data Rate (DDR) Interface
      3. 7.3.3 Micromirror Switching Control
      4. 7.3.4 DMD Voltage Supplies
      5. 7.3.5 Logic Reset
      6. 7.3.6 Temperature Sensing Diode
        1. 7.3.6.1 Temperature Sense Diode Theory
      7. 7.3.7 Active Array Temperature
      8. 7.3.8 DMD JTAG Interface
    4. 7.4 Optical Performance
      1. 7.4.1 Numerical Aperture and Stray Light Control
      2. 7.4.2 Pupil Match
      3. 7.4.3 Illumination Overfill and Alignment
    5. 7.5 DMD Image Quality Specification
    6. 7.6 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 HUD Reference Design and LED Controller Reference Design
    3. 8.3 Application Mission Profile Consideration
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Sequencing Requirements
      1. 9.1.1 Power Up and Power Down
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Temperature Diode Pins
    3. 10.3 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 器件命名规则
      2. 11.1.2 器件标记
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 器件处理
    8. 11.8 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.3.2 Double Data Rate (DDR) Interface

Each DMD micromirror and its associated SRAM memory cell is loaded with data from the DLPC120-Q1 via the DDR interface (DATA(14:0), DCLK, LOADB, SCRTL, and TRC). These signals are low voltage CMOS nominally operating at 1.8-V level to reduce power and switching noise. This high speed data input to the DMD allows for a maximum update rate of the entire micromirror array to be nearly 5 kHz, enabling the creation of seamless digital images using Pulse Width Modulation (PWM).