ZHCSEV4A February   2016  – March 2016 DAC8551-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 DAC Section
        1. 7.3.1.1 Resistor String
        2. 7.3.1.2 Output Amplifier
      2. 7.3.2 Power-On Reset
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Down Modes
    5. 7.5 Programming
      1. 7.5.1 SYNC Interrupt
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Loop-Powered 2-Wire 4-mA to 20-mA Transmitter With XTR116
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Bipolar Operation Using the DAC8551-Q1
      3. 8.2.3 Using the REF02 As a Power Supply for the DAC8551-Q1
    3. 8.3 System Examples
      1. 8.3.1 Interface from DAC8551-Q1 to 8051
      2. 8.3.2 Interface from DAC8551-Q1 to Microwire
      3. 8.3.3 Interface from DAC8551-Q1 to 68HC11
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档　
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VDD to GND –0.3 6 V
Digital input voltage to GND DIN, SCLK and SYNC –0.3 VDD + 0.3 V
VOUT to GND –0.3 VDD + 0.3 V
VREF to GND –0.3 VDD + 0.3 V
VFB to GND –0.3 VDD + 0.3 V
Junction temperature range, TJ max –65 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2000 V
Charged-device model (CDM), per AEC Q100-011 All pins ±500
Corner pins (1, 4, 5, and 8) ±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)
MIN NOM MAX UNIT
POWER SUPPLY
Supply voltage VDD to GND 3.2 5.5 V
DIGITAL INPUTS
Digital input voltage DIN, SCLK and SYNC 0 VDD V
REFERENCE INPUT
VREF Reference input voltage 0 VDD V
AMPLIFIER FEEDBACK INPUT
VFB Output amplifier feedback input VOUT V
TEMPERATURE RANGE
TA Operating ambient temperature –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) DAC8551-Q1 UNIT
DGK (VSSOP)
8 PINS
RθJA Junction-to-ambient thermal resistance 173.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 94.2 °C/W
RθJB Junction-to-board thermal resistance 65.4 °C/W
ψJT Junction-to-top characterization parameter 10.2 °C/W
ψJB Junction-to-board characterization parameter 92.7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

VDD = 3.2 V to 5.5 V, VREF = VDD and TA = –40°C to 125°C, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE(1)
Resolution 16 Bits
Relative accuracy ±4 ±16 LSB
Differential nonlinearity ±0.35 ±2 LSB
Offset error ±1 ±15 mV
Full-scale error ±0.05 ±0.5 % of FSR
Gain error ±0.02 ±0.2 % of FSR
Offset error drift ±5 μV/°C
Gain temperature coefficient ±1 ppm of FSR/°C
PSRR Power-supply rejection ratio RL = 2 kΩ, CL = 200 pF 0.75 mV/V
OUTPUT CHARACTERISTICS(2)
Output voltage range 0 VREF V
Output voltage settling time To ±0.003% FSR, 0200h to FD00h
RL = 2 kΩ, 0 pF < CL < 200 pF		 8 μs
Slew rate 1.4 V/μs
Capacitive load stability RL = ∞ 470 pF
RL = 2 kΩ 1000 pF
Code change glitch impulse 1 LSB change around major carry 0.1 nV-s
Digital feedthrough 50 kΩ series resistance on digital lines 0.1 nV-s
DC output impedance At mid-code input 1 Ω
Short-circuit current VDD = 3.2 V to 5.5 V 35 mA
AC PERFORMANCE
SNR Signal-to-noise ratio BW = 20 kHz, VDD = 5 V, VREF = 4.5 V, fOUT = 1 kHz
First 19 harmonics removed for SNR calculation		 84 dB
THD Total harmonic distortion –80 dB
SFDR Spurious-free dynamic range 84 dB
SINAD Signal to noise and distortion 76 dB
REFERENCE INPUT
Reference current VREF = VDD = 5.5 V 50 μA
VREF = VDD = 3.6 V 25
Reference input range 0 VDD V
Reference input impedance 125 kΩ
LOGIC INPUTS(2)
Input current ±1 μA
VINL Input low voltage VDD = 5 V 0.3×VDD V
VDD = 3.3 V 0.1×VDD
VINH Input high voltage VDD = 5 V 0.7×VDD V
VDD = 3.3 V 0.9×VDD
Pin capacitance 3 pF
POWER REQUIREMENTS
VDD Supply voltage 3.2 5.5 V
IDD Supply current Normal mode, input code = 32,768, no load, does not include reference current. VIH = VDD and VIL = GND,
VDD = 3.6 V to 5.5 V		 160 250 μA
Normal mode, input code = 32,768, no load, does not include reference current. VIH = VDD and VIL = GND,
VDD = 3.2 V to 3.6 V		 110 240
All power-down modes, VIH = VDD and VIL = GND,
VDD = 3.6 V to 5.5 V		 0.8 3
All power-down modes, VIH = VDD and VIL = GND,
VDD = 3.2 V to 3.6 V		 0.5 3
POWER EFFICIENCY
IOUT / IDD ILOAD = 2 mA, VDD = 5 V 89%
TEMPERATURE RANGE
TA Ambient temperature –40 125 °C
(1) Linearity calculated using a reduced code range of 485 to 64,741; output unloaded.
(2) Specified by design and characterization; not production tested.

6.6 Timing Requirements(1)(2)

VDD = 3.2 V to 5.5 V and TA = –40°C to 125°C, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
fSCLK Serial clock frequency VDD = 3.2 V to 3.6 V 25 MHz
VDD = 3.6 V to 5.5 V 30
t1 SCLK cycle time VDD = 3.2 V to 3.6 V 40 ns
VDD = 3.6 V to 5.5 V 34
t2 SCLK high time VDD = 3.2 V to 3.6 V 13 ns
VDD = 3.6 V to 5.5 V 13
t3 SCLK low time VDD = 3.2 V to 3.6 V 22.5 ns
VDD = 3.6 V to 5.5 V 13
t4 SYNC to SCLK rising edge setup time VDD = 3.2 V to 3.6 V 0 ns
VDD = 3.6 V to 5.5 V 0
t5 Data setup time VDD = 3.2 V to 3.6 V 5 ns
VDD = 3.6 V to 5.5 V 5
t6 Data hold time VDD = 3.2 V to 3.6 V 5 ns
VDD = 3.6 V to 5.5 V 5
t7 24th SCLK falling edge to SYNC rising edge VDD = 3.2 V to 3.6 V 0 ns
VDD = 3.6 V to 5.5 V 0
t8 Minimum SYNC high time VDD = 3.2 V to 3.6 V 50 ns
VDD = 3.6 V to 5.5 V 34
t9 24th SCLK falling edge to SYNC falling edge VDD = 3.2 V to 5.5 V 50 ns
(1) All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH) / 2.

6.7 Switching Characteristics

over operating ambient temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power-up time Coming out of power-down mode, VDD = 5 V 2.5 µs
Coming out of power-down mode, VDD = 3.3 V 5
DAC8551-Q1 tim_ser_las430.gif Figure 1. Serial-Write-Operation Timing Diagram

6.8 Typical Characteristics

At TA = 25°C, VDD = 5 V unless otherwise noted.
DAC8551-Q1 tc_le_5v_40c_las429.gif Figure 2. Linearity Error and Differential Linearity Error vs Digital Input Code (–40°C)
DAC8551-Q1 tc_le_5v_105c_las429.gif Figure 4. Linearity Error and Differential Linearity Error vs Digital Input Code (125°C)
DAC8551-Q1 tc_fse-tmp_5v_SLASEB8.gif Figure 6. Full-Scale Error vs Temperature
DAC8551-Q1 tc_idd-code_5v_las429.gif Figure 8. Supply Current vs Digital Input Code
DAC8551-Q1 tc_idd-vdd_5v_SLASEB8.gif Figure 10. Supply Current vs Supply Voltage
DAC8551-Q1 tc_idd-logic_5v_las429.gif Figure 12. Supply Current vs Logic Input Voltage
DAC8551-Q1 tc_fs_5v_fal_las429.gif Figure 14. Full-Scale Settling Time: 5-V Falling Edge
DAC8551-Q1 tc_hs_5v_fal_las429.gif Figure 16. Half-Scale Settling Time: 5-V Falling Edge
DAC8551-Q1 tc_gl_5v1_fal_las429.gif Figure 18. Glitch Impulse: 5 V, 1-LSB Step, Falling Edge
DAC8551-Q1 tc_gl_5v16_fal_las429.gif Figure 20. Glitch Impulse: 5 V, 16-LSB Step, Falling Edge
DAC8551-Q1 tc_gl_5v256_fal_las429.gif Figure 22. Glitch Impulse: 5 V, 256-LSB Step, Falling Edge
DAC8551-Q1 tc_snr-fout_5v_las429.gif Figure 24. Signal-to-Noise Ratio vs Output Frequency
DAC8551-Q1 tc_noise_density_5v_las429.gif Figure 26. Output Noise Density
DAC8551-Q1 tc_le_5v_25c_las429.gif Figure 3. Linearity Error and Differential Linearity Error vs Digital Input Code (25°C)
DAC8551-Q1 tc_zse-tmp_5v_SLASEB8.gif Figure 5. Offset Error vs Temperature
DAC8551-Q1 tc_source_sink_5v_las429.gif Figure 7. Source and Sink Current Capability
DAC8551-Q1 tc_idd-tmp_5v_SLSAEB8.gif Figure 9. Power-Supply Current vs Temperature
DAC8551-Q1 tc_pd-vdd_5v_SLASEB8.gif Figure 11. Power-Down Current vs Supply Voltage
DAC8551-Q1 tc_fs_5v_ris_las429.gif Figure 13. Full-Scale Settling Time: 5-V Rising Edge
DAC8551-Q1 tc_hs_5v_ris_las429.gif Figure 15. Half-Scale Settling Time: 5-V Rising Edge
DAC8551-Q1 tc_gl_5v1_ris_las429.gif Figure 17. Glitch Impulse: 5 V, 1-LSB Step, Rising Edge
DAC8551-Q1 tc_gl_5v16_ris_las429.gif Figure 19. Glitch Impulse: 5 V, 16-LSB Step, Rising Edge
DAC8551-Q1 tc_gl_5v256_ris_las429.gif Figure 21. Glitch Impulse: 5 V, 256-LSB Step, Rising Edge
DAC8551-Q1 tc_thd-fout_5v_las429.gif Figure 23. Total Harmonic Distortion vs Output Frequency
DAC8551-Q1 tc_power_density_5v_las429.gif Figure 25. Power Spectral Density