Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The DAC38RF8xx device family can be used in RF transmitters designed to support multiple operating bands. The two transmit antennae system shown in Figure 168 uses DAC38RF8xx to convert digital baseband signals from an FPGA directly to RF signals in LTE downlink band 1 (2110 MHz - 2170 MHz) and band 3 (1805 MHz - 1880 MHz).
|Operating bands||Band 1 (2110 MHz - 2170 MHz) and Band 3 (1805 MHz to 1880 MHz)|
|Data rate (baseband)||368.64 MHz|
|Sampling frequency||8847.36 MHz|
|JESD204B Interface configuration||L-M-F-S-Hd = 8-8-2-1-0|
Two complex data streams of 20MHz LTE data generated in a baseband processor (FPGA/ASIC) is formatted based on Table 18and transmitted to DAC38RF8xx. Inside DAC38RF8xx, the complex input data at a rate of 368.64 MSPS is interpolated 24 times to the final output sampling rate of 8847.36 MSPS. This enables the final RF output to be positioned in the first Nyquist zone for minimal attenuation due to sinc(x) roll off. After interpolation, the output complex data stream is digitally mixed to the final RF frequencies. The digital mixing eliminates system imperfections such as local oscillator (LO) feed-through and sideband images that are inherent in analog mixers. Detailed block diagram is shown in (Figure 169)
To simplify the system clocking, a low frequency clock (or device clock) is provided as a reference to the on-chip PLL (Internal PLL/VCO) of DAC38RF8xx. The PLL generates a low phase noise, high frequency sampling clock from the low frequency reference.
SerDes rate = 1.25 x (M/L) x Baseband data rate x Number of bits per sample (16)
M is a JESD204B interface parameter that refers to the number of data streams from FPGA to DAC
L is a JESD204B interface parameter that refers to the number of SerDes lanes used to transmit data
1.25 is a factor due to the 8B10B encoding of the baseband data
if the baseband data rate = 368.64 MSPS and L-M-F-S-Hd = 8-8-2-1-0
Valid SYSREF frequencies depend on the following parameters:
Maximum SYSREF frequency = (Sample clock frequency/N),
where N =LCM(CLKJESD_DIV,4 x K x F). N is the Least common multiple of 4 x K x F and CLKJESD_DIV.
All valid SYSREF frequencies are integer divisors of the maximum SYSREF frequency.
Given sampling clock frequency = 8.84736 GSPS, Interpolation = 24, DAC Mode=L-M-F-S=8-8-2-1 and K=20:
CLKJESD_DIV = 24 (CLKJESD_DIV)
Maximum SYSREF Frequency = 8847.36 MHz/240 = 36.864 MHz
Valid SYSREF Frequencies = 36.864 MHz/n, where n is any positive integer.