ZHCSJC1D April   2019  – May 2021 CC3235S , CC3235SF

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 功能方框图
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Pin Attributes
      1.      11
    3. 7.3 Signal Descriptions
      1.      13
    4. 7.4 Pin Multiplexing
    5. 7.5 Drive Strength and Reset States for Analog and Digital Multiplexed Pins
    6. 7.6 Pad State After Application of Power to Device, Before Reset Release
    7. 7.7 Connections for Unused Pins
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Power-On Hours (POH)
    4. 8.4  Recommended Operating Conditions
    5. 8.5  Current Consumption Summary (CC3235S)
      1.      24
      2.      25
    6. 8.6  Current Consumption Summary (CC3235SF)
      1.      27
      2.      28
    7. 8.7  TX Power Control for 2.4 GHz Band
    8. 8.8  TX Power Control for 5 GHz
    9. 8.9  Brownout and Blackout Conditions
    10. 8.10 Electrical Characteristics for GPIO Pins
      1.      33
      2.      34
    11. 8.11 Electrical Characteristics for Pin Internal Pullup and Pulldown
    12. 8.12 WLAN Receiver Characteristics
      1.      37
      2.      38
    13. 8.13 WLAN Transmitter Characteristics
      1.      40
      2.      41
    14. 8.14 WLAN Transmitter Out-of-Band Emissions
      1.      43
      2.      44
    15. 8.15 BLE/2.4 GHz Radio Coexistence and WLAN Coexistence Requirements
    16. 8.16 Thermal Resistance Characteristics for RGK Package
    17. 8.17 Timing and Switching Characteristics
      1. 8.17.1 Power Supply Sequencing
      2. 8.17.2 Device Reset
      3. 8.17.3 Reset Timing
        1. 8.17.3.1 nRESET (32-kHz Crystal)
        2.       52
        3.       53
        4. 8.17.3.2 nRESET (External 32-kHz Clock)
          1.        55
      4. 8.17.4 Wakeup From HIBERNATE Mode
      5. 8.17.5 Clock Specifications
        1. 8.17.5.1 Slow Clock Using Internal Oscillator
        2. 8.17.5.2 Slow Clock Using an External Clock
          1.        60
        3. 8.17.5.3 Fast Clock (Fref) Using an External Crystal
          1.        62
        4. 8.17.5.4 Fast Clock (Fref) Using an External Oscillator
          1.        64
      6. 8.17.6 Peripherals Timing
        1. 8.17.6.1  SPI
          1. 8.17.6.1.1 SPI Master
            1.         68
          2. 8.17.6.1.2 SPI Slave
            1.         70
        2. 8.17.6.2  I2S
          1. 8.17.6.2.1 I2S Transmit Mode
            1.         73
          2. 8.17.6.2.2 I2S Receive Mode
            1.         75
        3. 8.17.6.3  GPIOs
          1. 8.17.6.3.1 GPIO Output Transition Time Parameters (Vsupply = 3.3 V)
            1.         78
          2. 8.17.6.3.2 GPIO Input Transition Time Parameters
            1.         80
        4. 8.17.6.4  I2C
          1.        82
        5. 8.17.6.5  IEEE 1149.1 JTAG
          1.        84
        6. 8.17.6.6  ADC
          1.        86
        7. 8.17.6.7  Camera Parallel Port
          1.        88
        8. 8.17.6.8  UART
        9. 8.17.6.9  SD Host
        10. 8.17.6.10 Timers
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  Arm® Cortex®-M4 Processor Core Subsystem
    3. 9.3  Wi-Fi® Network Processor Subsystem
      1. 9.3.1 WLAN
      2. 9.3.2 Network Stack
    4. 9.4  Security
    5. 9.5  FIPS 140-2 Level 1 Certification
    6. 9.6  Power-Management Subsystem
    7. 9.7  Low-Power Operating Mode
    8. 9.8  Memory
      1. 9.8.1 External Memory Requirements
      2. 9.8.2 Internal Memory
        1. 9.8.2.1 SRAM
        2. 9.8.2.2 ROM
        3. 9.8.2.3 Flash Memory
        4. 9.8.2.4 Memory Map
    9. 9.9  Restoring Factory Default Configuration
    10. 9.10 Boot Modes
      1. 9.10.1 Boot Mode List
    11. 9.11 Hostless Mode
  10. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
      1. 10.1.1 BLE/2.4 GHz Radio Coexistence
      2. 10.1.2 Antenna Selection
      3. 10.1.3 Typical Application
    2. 10.2 PCB Layout Guidelines
      1. 10.2.1 General PCB Guidelines
      2. 10.2.2 Power Layout and Routing
        1. 10.2.2.1 Design Considerations
      3. 10.2.3 Clock Interface Guidelines
      4. 10.2.4 Digital Input and Output Guidelines
      5. 10.2.5 RF Interface Guidelines
  11. 11Device and Documentation Support
    1. 11.1  第三方产品免责声明
    2. 11.2  Tools and Software
    3. 11.3  Firmware Updates
    4. 11.4  Device Nomenclature
    5. 11.5  Documentation Support
    6. 11.6  Related Links
    7. 11.7  支持资源
    8. 11.8  Trademarks
    9. 11.9  静电放电警告
    10. 11.10 Export Control Notice
    11. 11.11 术语表
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Packaging Information
      1. 12.1.1 Package Option Addendum
        1. 12.1.1.1 Packaging Information
        2. 12.1.1.2 Tape and Reel Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Table 7-1 Pin Descriptions
PINS TYPE DESCRIPTION SELECT AS WAKEUP SOURCE CONFIGURE ADDITIONAL ANALOG MUX MUXED WITH JTAG
NO. NAME
1 GPIO10 I/O General-purpose input or output No No No
2 GPIO11 I/O General-purpose input or output Yes No No
3 GPIO12 I/O General-purpose input or output No No No
4 GPIO13 I/O General-purpose input or output Yes No No
5 GPIO14 I/O General-purpose input or output No No No
6 GPIO15 I/O General-purpose input or output No No No
7 GPIO16 I/O General-purpose input or output No No No
8 GPIO17 I/O General-purpose input or output Yes No No
9 VDD_DIG1 Power Internal digital core voltage N/A N/A N/A
10 VIN_IO1 Power I/O power supply (same as battery voltage) N/A N/A N/A
11 FLASH_SPI_CLK O Serial flash interface: SPI clock N/A N/A N/A
12 FLASH_SPI_DOUT O Serial flash interface: SPI data out N/A N/A N/A
13 FLASH_SPI_DIN I Serial flash interface: SPI data in N/A N/A N/A
14 FLASH_SPI_CS O Serial flash interface: SPI chip select N/A N/A N/A
15 GPIO22 I/O General-purpose input or output No No No
16 TDI I/O JTAG interface: data input No No Muxed with JTAG TDI
17 TDO I/O JTAG interface: data output Yes No Muxed with JTAG TDO
18 GPIO28 I/O General-purpose input or output No No No
19 TCK I/O JTAG / SWD interface: clock No No Muxed with JTAG/
SWD-TCK
20 TMS I/O JTAG / SWD interface: mode select or SWDIO No No Muxed with JTAG/
SWD-TMSC
21(1) SOP2 O Configuration sense-on-power No No No
22 WLAN_XTAL_N Analog 40-MHz XTAL N/A N/A N/A
23 WLAN_XTAL_P Analog 40-MHz XTAL or TCXO clock input N/A N/A N/A
24 VDD_PLL Power Internal analog voltage N/A N/A N/A
25 LDO_IN2 Power Analog RF supply from analog DCDC output N/A N/A N/A
26 NC — No Connect N/A N/A N/A
27 A_RX RF RF A band: 5 GHz A_RX N/A N/A N/A
28 A_TX RF RF A band: 5 GHz A_TX N/A N/A N/A
29 GND GND Ground N/A N/A N/A
30 GND GND Ground N/A N/A N/A
31 RF_BG RF RF BG band: 2.4 GHz TX, RX N/A N/A N/A
32 nRESET I Master chip reset input. Active low input. N/A N/A N/A
33 VDD_PA_IN Power RF power amplifier (PA) input from PA DC-DC output N/A N/A N/A
34 SOP1 O Configuration sense-on-power and 5 GHz switch control N/A N/A N/A
35 SOP0 O Configuration sense-on-power and 5 GHz switch control N/A N/A N/A
36 LDO_IN1 Power Analog RF supply from analog DCDC output N/A N/A N/A
37 VIN_DCDC_ANA Power Analog DC-DC supply input (same as battery voltage) N/A N/A N/A
38 DCDC_ANA_SW Power Analog DC/DC converter switching node N/A N/A N/A
39 VIN_DCDC_PA Power PA DC/DC converter input supply (same as battery voltage) N/A N/A N/A
40 DCDC_PA_SW_P Power PA DC/DC converter +ve switching node N/A N/A N/A
41 DCDC_PA_SW_N Power PA DC/DC converter –ve switching node N/A N/A N/A
42 DCDC_PA_OUT Power PA DC/DC converter output. N/A N/A N/A
43 DCDC_DIG_SW Power Digital DC/DC converter switching node N/A N/A N/A
44 VIN_DCDC_DIG Power Digital DC/DC converter supply input (same as battery voltage) N/A N/A N/A
45 DCDC_ANA2_SW_P I/O Analog2 DCDC converter +ve switching node No User configuration not required (2) No
46 DCDC_ANA2_SW_N Power Analog2 DC-DC converter -ve switching node N/A N/A N/A
47 VDD_ANA2 Power Analog2 DC-DC output N/A N/A N/A
48 VDD_ANA1 Power Analog1 power supply fed by ANA2 DC-DC output N/A N/A N/A
49 VDD_RAM Analog SRAM LDO output N/A N/A N/A
50 GPIO0 I/O General-purpose input or output No User configuration not required (2) No
51 RTC_XTAL_P Analog 32.768-kHz XTAL_P or external CMOS level clock input N/A N/A N/A
52 RTC_XTAL_N Analog 32.768-kHz XTAL_N N/A User configuration not required (2)(3) No
53 GPIO30 I/O General-purpose input or output No User configuration not required (2) No
54 VIN_IO2 Analog Chip supply voltage (VBAT) N/A N/A N/A
55 GPIO1 I/O General-purpose input or output No No No
56 VDD_DIG2 Analog Internal digital core voltage N/A N/A N/A
57 GPIO2 I/O Analog input (1.5V max) or general-purpose input or output Wake-up source See (4) No
58 GPIO3 I/O Analog input (1.5V max) or general-purpose input or output No See (4) No
59 GPIO4 I/O Analog input (1.5V max) or general-purpose input or output Wake-up source See (4) No
60 GPIO5 I/O Analog input (1.5V max) or general-purpose input or output No See (4) No
61 GPIO6 I/O General-purpose input or output No No No
62 GPIO7 I/O General-purpose input or output No No No
63 GPIO8 I/O General-purpose input or output No No No
64 GPIO9 I/O General-purpose input or output No No No
GND_TAB — Thermal pad and electrical ground N/A N/A N/A
(1) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.
(2) Device firmware automatically enables the digital path during ROM boot.
(3) To use the digital functions, RTC_XTAL_N must be pulled high to the supply voltage using a 100-kΩ resistor.
(4) Requires user configuration to enable the analog switch of the ADC channel (the switch is off by default.) The digital I/O is always connected and must be made Hi-Z before enabling the ADC switch.

 

Table 7-2 Pin Attributes
PIN NO. SIGNAL NAME(1) SIGNAL TYPE(2) PIN MUX ENCODING SIGNAL DIRECTION PAD STATES
LPDS(3) Hib(4) nRESET = 0
1 GPIO10 (PN) I/O 0 I/O Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z
I2C_SCL 1 I/O (open drain) Hi-Z, Pull, Drive
GT_PWM06 3 O Hi-Z, Pull, Drive
UART1_TX 7 O 1
SDCARD_CLK 6 O 0
GT_CCP01 12 I Hi-Z, Pull, Drive
2 GPIO11 (PN) I/O 0 I/O Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z
I2C_SDA 1 I/O (open drain) Hi-Z, Pull, Drive
GT_PWM07 3 O Hi-Z, Pull, Drive
pXCLK(XVCLK) 4 O 0
SDCARD_CMD 6 I/O (open drain) Hi-Z, Pull, Drive
UART1_RX 7 I Hi-Z, Pull, Drive
GT_CCP02 12 I Hi-Z, Pull, Drive
MCAFSX 13 O Hi-Z, Pull, Drive
3 GPIO12 (PN) I/O 0 I/O Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z
McACLK 3 O Hi-Z, Pull, Drive
pVS(VSYNC) 4 I Hi-Z, Pull, Drive
I2C_SCL 5 I/O (open drain) Hi-Z, Pull, Drive
UART0_TX 7 O 1
GT_CCP03 12 I Hi-Z, Pull, Drive
4 GPIO13 (PN) I/O 0 I/O Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z
I2C_SDA 5 I/O (open drain)
pHS(HSYNC) 4 I
UART0_RX 7 I
GT_CCP04 12 I
5 GPIO14 (PN) I/O 0 I/O Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z
I2C_SCL 5 I/O (open drain)
GSPI_CLK 7 I/O
pDATA8(CAM_D4) 4 I
GT_CCP05 12 I
6 GPIO15 (PN) I/O 0 I/O Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z
I2C_SDA 5 I/O (open drain)
GSPI_MISO 7 I/O
pDATA9(CAM_D5) 4 I
GT_CCP06 13 I
SDCARD_ DATA0 8 I/O
7 GPIO16 (PN) I/O 0 I/O Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z
GSPI_MOSI 7 I/O Hi-Z, Pull, Drive
pDATA10(CAM_D6) 4 I Hi-Z, Pull, Drive
UART1_TX 5 O 1
GT_CCP07 13 I Hi-Z, Pull, Drive
SDCARD_CLK 8 O 0
8 GPIO17 (PN) I/O 0 I/O Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z
UART1_RX 5 I
GSPI_CS 7 I/O
pDATA11 (CAM_D7) 4 I
SDCARD_ CMD 8 I/O
9 VDD_DIG1 (PN) — N/A N/A N/A N/A N/A
10 VIN_IO1 — N/A N/A N/A N/A N/A
11 FLASH_SPI_CLK O N/A O Hi-Z, Pull, Drive(5) Hi-Z, Pull, Drive Hi-Z
12 FLASH_SPI_DOUT O N/A O Hi-Z, Pull, Drive(5) Hi-Z, Pull, Drive Hi-Z
13 FLASH_SPI_DIN I N/A I Hi-Z, Pull, Drive(5) Hi-Z Hi-Z
14 FLASH_SPI_CS O N/A O 1 Hi-Z, Pull, Drive Hi-Z
15 GPIO22 (PN) I/O 0 I/O Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z
McAFSX 7 O
GT_CCP04 5 I
16 TDI (PN) I/O 1 I Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z
GPIO23 0 I/O
UART1_TX 2 O 1
I2C_SCL 9 I/O (open drain) Hi-Z, Pull, Drive
17 TDO (PN) I/O 1 O Hi-Z, Pull, Drive Driven high in SWD; driven low in 4-wire JTAG Hi-Z
GPIO24 0 I/O
PWM0 5 O
UART1_RX 2 I
I2C_SDA 9 I/O (open drain)
GT_CCP06 4 I
McAFSX 6 O
18 GPIO28 (PN) I/O 0 I/O Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z
19 TCK (PN) I/O 1 I Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z
GT_PWM03 8 O
20 TMS (PN) I/O 1 I/O Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z
GPIO29 0 I/O
21(6) GPIO25 O 0 O Hi-Z, Pull, Drive Driven low Hi-Z
GT_PWM02 9 O Hi-Z, Pull, Drive
McAFSX 2 O Hi-Z, Pull, Drive
TCXO_EN N/A O 0
SOP2 (PN) See (7) I Hi-Z, Pull, Drive
22 WLAN_XTAL_N — N/A N/A N/A N/A N/A
23 WLAN_XTAL_P — N/A N/A N/A N/A N/A
24 VDD_PLL — N/A N/A N/A N/A N/A
25 LDO_IN2 — N/A N/A N/A N/A N/A
26 NC — N/A N/A N/A N/A N/A
27 A_RX — N/A N/A N/A N/A N/A
28 A_TX — N/A N/A N/A N/A N/A
29 GND — N/A N/A N/A N/A N/A
30 GND — N/A N/A N/A N/A N/A
31 RF_BG — N/A N/A N/A N/A N/A
32 nRESET — N/A N/A N/A N/A N/A
33 VDD_PA_IN — N/A N/A N/A N/A N/A
34(8) SOP1 (PN) I/O N/A N/A N/A N/A N/A
A_SC1 N/A N/A N/A N/A N/A
35(8) SOP0 (PN) I/O N/A N/A N/A N/A N/A
A_SC2 N/A N/A N/A N/A N/A
36 LDO_IN1 — N/A N/A N/A N/A N/A
37 VIN_DCDC_ANA — N/A N/A N/A N/A N/A
38 DCDC_ANA_SW — N/A N/A N/A N/A N/A
39 VIN_DCDC_PA — N/A N/A N/A N/A N/A
40 DCDC_PA_SW_P — N/A N/A N/A N/A N/A
41 DCDC_PA_SW_N — N/A N/A N/A N/A N/A
42 DCDC_PA_OUT — N/A N/A N/A N/A N/A
43 DCDC_DIG_SW — N/A N/A N/A N/A N/A
44 VIN_DCDC_DIG — N/A N/A N/A N/A N/A
45(9) GPIO31 I/O 0 I/O Hi-Z Hi-Z Hi-Z
UART0_RX 9 I
McAFSX 12 O
UART1_RX 2 I
McAXR0 6 I/O
GSPI_CLK 7 I/O
DCDC_ANA2_SW_P (PN) — See (10) N/A N/A N/A N/A
46 DCDC_ANA2_SW_N — N/A N/A N/A N/A N/A
47 VDD_ANA2 — N/A N/A N/A N/A N/A
48 VDD_ANA1 — N/A N/A N/A N/A N/A
49 VDD_RAM — N/A N/A N/A N/A N/A
50 GPIO0 (PN) I/O 0 I/O Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z
UART0_CTS 12 I Hi-Z, Pull, Drive
McAXR1 6 I/O Hi-Z, Pull, Drive
GT_CCP00 7 I Hi-Z, Pull, Drive
GSPI_CS 9 I/O Hi-Z, Pull, Drive
UART1_RTS 10 O 1
UART0_RTS 3 O 1
McAXR0 4 I/O Hi-Z, Pull, Drive
51 RTC_XTAL_P — N/A N/A N/A N/A N/A
52(11) RTC_XTAL_N (PN) O N/A N/A N/A Hi-Z, Pull, Drive Hi-Z
GPIO32 0 O Hi-Z, Pull, Drive
McACLK 2 O
McAXR0 4 O
UART0_RTS 6 O 1
GSPI_MOSI 8 O Hi-Z, Pull, Drive
53 GPIO30 (PN) I/O 0 I/O Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z
UART0_TX 9 O 1
McACLK 2 O Hi-Z, Pull, Drive
McAFSX 3 O
GT_CCP05 4 I
GSPI_MISO 7 I/O
54 VIN_IO2 — N/A N/A N/A N/A N/A
55 GPIO1 (PN) I/O 0 I/O Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z
UART0_TX 3 O 1
pCLK (PIXCLK) 4 I Hi-Z, Pull, Drive
UART1_TX 6 O 1
GT_CCP01 7 I Hi-Z, Pull, Drive
56 VDD_DIG2 — N/A N/A N/A N/A N/A
57(12) ADC_CH0 Analog input (up to 1.5 V) or digital I/O See (10) I Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z
GPIO2 (PN) 0 I/O
UART0_RX 3 I
UART1_RX 6 I
GT_CCP02 7 I
58(12) ADC_CH1 Analog input (up to 1.5 V) or digital I/O See (10) I Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z
GPIO3 (PN) 0 I/O
UART1_TX 6 O 1
pDATA7 (CAM_D3) 4 I Hi-Z, Pull, Drive
59(12) ADC_CH2 Analog input (up to 1.5 V) or digital I/O See (10) I Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z
GPIO4 (PN) 0 I/O
UART1_RX 6 I
pDATA6 (CAM_D2) 4 I
60(12) ADC_CH3 Analog input (up to 1.5 V) or digital I/O See (10) I Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z
GPIO5 (PN) 0 I/O
pDATA5 (CAM_D1) 4 I
McAXR1 6 I/O
GT_CCP05 7 I
61 GPIO6 (PN) I/O 0 I/O Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z
UART0_RTS 5 O 1
pDATA4 (CAM_D0) 4 I Hi-Z, Pull, Drive
UART1_CTS 3 I
UART0_CTS 6 I
GT_CCP06 7 I
62 GPIO7 (PN) I/O 0 I/O Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z
McACLKX 13 O
UART1_RTS 3 O 1
UART0_RTS 10 O
UART0_TX 11 O
63 GPIO8 (PN) I/O 0 I/O Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z
SDCARD_IRQ 6 I
McAFSX 7 O
GT_CCP06 12 I
64 GPIO9 (PN) I/O 0 I/O Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z
GT_PWM05 3 O
SDCARD_DATA0 6 I/O
McAXR0 7 I/O
GT_CCP00 12 I
GND_TAB — N/A N/A N/A N/A N/A
(1) Signals names with (PN) denote the default pin name.
(2) Signal Types: I = Input, O = Output, I/O = Input or Output.
(3) LPDS state: Unused I/Os are in a Hi-Z state. Software may program the I/Os to be input with pull or drive (regardless of active pin configuration), according to the need.
(4) Hibernate mode: The I/Os are in a Hi-Z state. Software may program the I/Os to be input with pull or drive (regardless of active pin configuration), according to the need.
(5) To minimize leakage in some serial flash vendors during LPDS, TI recommends that the user application always enables internal weak pulldown resistors on the FLASH_SPI_DIN, FLASH_SPI_DOUT, and FLASH_SPI_CLK pins.
(6) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.
(7) This pin is one of three that must have a passive pullup or pulldown resistor onboard to configure the device hardware power-up mode. For this reason, the pin must be output only when used for digital functions.
(8) This pin has dual functions: as a SOP (device operation mode) input pin during boot up, and as the 5 GHz switch control (output) pin on power up
(9) Pin 45 is used by an internal DC/DC (ANA2_DCDC). For CC3235S device, pin 45 can be used as GPIO_31 if a supply is provided on pin 47.
(10) For details on proper use, see Section 7.5.
(11) Pin 52 is used by the RTC crystal oscillator. These devices use automatic configuration sensing. Therefore, some board-level configuration is required to use pin 52 as a digital pad. Pin 52 is used for RTC crystal in most applications. However, in some applications a 32.768-kHz square-wave clock might always be available onboard. When a 32.768-kHz square-wave clock is available, the crystal can be removed to free pin 52 for digital functions. The external clock must then be applied at pin 51. For the chip to automatically detect this configuration, a 100-kΩ pullup resistor must be connected between pin 52 and the supply line. To prevent false detection, TI recommends using pin 52 for output-only functions.
(12) This pin is shared by the ADC inputs and digital I/O pad cells.