ZHCSCJ6C June   2013  – June 2014 CC3100

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用范围
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2修订历史记录
  3. 3Terminal Configuration and Functions
    1. 3.1 Pin Attributes
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  Handling Ratings
    3. 4.3  Power-On Hours
    4. 4.4  Recommended Operating Conditions
    5. 4.5  Electrical Characteristics
    6. 4.6  WLAN Receiver Characteristics
    7. 4.7  WLAN Transmitter Characteristics
    8. 4.8  Current Consumption
    9. 4.9  Thermal Characteristics for RGC Package
    10. 4.10 Timing and Switching Characteristics
      1. 4.10.1 Power Supply Sequencing
      2. 4.10.2 Reset Timing
        1. 4.10.2.1 nRESET (32K XTAL)
        2. 4.10.2.2 nRESET (External 32K)
        3. 4.10.2.3 Wakeup from Hibernate
      3. 4.10.3 Clock Specifications
        1. 4.10.3.1 Slow Clock Using Internal Oscillator
        2. 4.10.3.2 Slow Clock Using an External Clock
        3. 4.10.3.3 Fast Clock (Fref) Using an External Crystal
        4. 4.10.3.4 Fast Clock (Fref) Using an External Oscillator
        5. 4.10.3.5 Input Clocks/Oscillators
      4. 4.10.4 Interfaces
        1. 4.10.4.1 Host SPI Interface Timing
        2. 4.10.4.2 Flash SPI Interface Timing
    11. 4.11 External Interfaces
      1. 4.11.1 SPI Flash Interface
      2. 4.11.2 SPI Host Interface
    12. 4.12 Host UART
      1. 4.12.1 5-Wire UART Topology
      2. 4.12.2 4-Wire UART Topology
      3. 4.12.3 3-Wire UART Topology
  5. 5Detailed Description
    1. 5.1 Overview
      1. 5.1.1 Device Features
        1. 5.1.1.1 WLAN
        2. 5.1.1.2 Network Stack
        3. 5.1.1.3 Host Interface and Driver
        4. 5.1.1.4 System
    2. 5.2 Functional Block Diagram
    3. 5.3 Wi-Fi Network Processor Subsystem
    4. 5.4 Power-Management Subsystem
      1. 5.4.1 VBAT Wide-Voltage Connection
      2. 5.4.2 Preregulated 1.85 V
    5. 5.5 Low-Power Operating Modes
      1. 5.5.1 Low-Power Deep Sleep
      2. 5.5.2 Hibernate
    6. 5.6 Memory
      1. 5.6.1 External Memory Requirements
  6. 6Applications and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Typical Application - CC3100 Wide-Voltage Mode
      2. 6.1.2 Typical Application - CC3100 Preregulated 1.85-V Mode
  7. 7器件和文档支持
    1. 7.1 器件支持
      1. 7.1.1 开发支持
        1. 7.1.1.1 射频工具
        2. 7.1.1.2 Uniflash 闪存编程器
      2. 7.1.2 器件命名规则
    2. 7.2 文档支持
    3. 7.3 社区资源
    4. 7.4 Trademarks
    5. 7.5 Electrostatic Discharge Caution
    6. 7.6 Glossary
  8. 8机械封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

3 Terminal Configuration and Functions

Figure 3-1 shows pin assignments for the 64-pin QFN package.

3x00_MOD-DEV_Symbol.gifFigure 3-1 QFN 64-Pin Assignments

3.1 Pin Attributes

Table 3-1 describes the CC3100 pins.

NOTE

If an external device drives a positive voltage to signal pads when the CC3100 device is not powered, DC current is drawn from the other device. If the drive strength of the external device is adequate, an unintentional wakeup and boot of the CC3100 device can occur. To prevent current draw, TI recommends one of the following:

  • All devices interfaced to the CC3100 device must be powered from the same power rail as the CC3100 device.
  • Use level-shifters between the CC3100 device and any external devices fed from other independent rails.
  • The nRESET pin of the CC3100 device must be held low until the VBAT supply to the device is driven and stable.

Table 3-1 Pin Attributes

PIN DEFAULT FUNCTION STATE AT RESET AND HIBERNATE I/O TYPE DESCRIPTION
1 NC Hi-Z N/A Unused; leave unconnected.
2 nHIB Hi-Z I Hibernate signal input to the NWP (active low). This is connected to the MCU GPIO. If the Hibernate function is not used, connect to Vcc using 100K pull-up.
3 Reserved Hi-Z NA Reserved for future use
4 FORCE_AP Hi-Z I For forced AP mode, pull to high on the board using 100k resistor. Otherwise, pull down to ground using 100k resistor.(1)
5 HOST_SPI_CLK Hi-Z I Host interface SPI clock
6 HOST_SPI_MOSI Hi-Z I Host interface SPI data input
7 HOST_SPI_MISO Hi-Z O Host interface SPI data output
8 HOST_SPI_CS Hi-Z I Host interface SPI chip select
9 VDD_DIG1 Hi-Z Power Digital core supply (1.2 V)
10 VIN_IO1 Hi-Z Power I/O supply
11 FLASH_SPI_CLK Hi-Z O Serial flash interface: SPI clock
12 FLASH_SPI_MOSI Hi-Z O Serial flash interface: SPI data out
13 FLASH _SPI_MISO
(active high)		 Hi-Z I Serial flash interface: SPI data in
14 FLASH _SPI_CS Hi-Z O Serial flash interface: SPI chip select
15 HOST_INTR Hi-Z O Interrupt output
16 NC Hi-Z N/A Unused; leave unconnected.
17 NC Hi-Z N/A Unused; leave unconnected.
18 NC Hi-Z N/A Unused; leave unconnected.
19 NC Hi-Z N/A Unused; leave unconnected.
20 NC Hi-Z N/A Unused; leave unconnected.
21 SOP2/TCXO_EN Hi-Z O Enable signal for external TCXO. Add 10k pulldown to ground.
22 WLAN_XTAL_N Hi-Z Analog Connect the WLAN 40-MHz XTAL here.
23 WLAN_XTAL_P Hi-Z Analog Connect the WLAN 40-MHz XTAL here.
24 VDD_PLL Hi-Z Power Internal PLL power supply (1.4 V nominal)
25 LDO_IN2 Hi-Z Power Input to internal LDO
26 NC Hi-Z N/A Unused; leave unconnected.
27 NC Hi-Z N/A Unused; leave unconnected.
28 NC Hi-Z N/A Unused; leave unconnected.
29 Reserved Hi-Z O Reserved for future use
30 Reserved Hi-Z O Reserved for future use
31 RF_BG Hi-Z RF 2.4-GHz RF TX/RX
32 nRESET Hi-Z I RESET input for the device. Active low input. Use RC circuit (100k || 0.1 µF) for power on reset.
33 VDD_PA_IN Hi-Z Power Power supply for the RF power amplifier (PA)
34 SOP1 Hi-Z N/A Add 100K pulldown to ground.
35 SOP0 Hi-Z N/A Add 100K pulldown to ground.
36 LDO_IN1 Hi-Z Power Input to internal LDO
37 VIN_DCDC_ANA Hi-Z Power Power supply for the DC-DC converter for analog section
38 DCDC_ANA_SW Hi-Z Power Analog DC-DC converter switch output
39 VIN_DCDC_PA Hi-Z Power PA DC-DC converter input supply
40 DCDC_PA_SW_P Hi-Z Power PA DC-DC converter switch output +ve
41 DCDC_PA_SW_N Hi-Z Power PA DC-DC converter switch output –ve
42 DCDC_PA_OUT Hi-Z Power PA DC-DC converter output. Connect the output capacitor for DC-DC here.
43 DCDC_DIG_SW Hi-Z Power Digital DC-DC converter switch output
44 VIN_DCDC_DIG Hi-Z Power Power supply input for the digital DC-DC converter
45 DCDC_ANA2_SW_P Hi-Z Power Analog2 DC-DC converter switch output +ve
46 DCDC_ANA2_SW_N Hi-Z Power Analog2 DC-DC converter switch output –ve
47 VDD_ANA2 Hi-Z Power Analog2 power supply input
48 VDD_ANA1 Hi-Z Power Analog1 power supply input
49 VDD_RAM Hi-Z Power Power supply for the internal RAM
50 UART1_nRTS Hi-Z O UART host interface
51 RTC_XTAL_P Hi-Z Analog 32.768 kHz XTAL_P/external CMOS level clock input
52 RTC_XTAL_N Hi-Z Analog 32.768 kHz XTAL_N/100k external pullup for external clock
53 NC Hi-Z N/A Unused. Leave unconnected.
54 VIN_IO2 Hi-Z Power I/O power supply. Same as battery voltage.
55 UART1_TX Hi-Z O UART host interface. Connect to test point on prototype for flash programming.
56 VDD_DIG2 Hi-Z Power Digital power supply (1.2 V)
57 UART1_RX Hi-Z I UART host interface. Connect to test point on prototype for flash programming.
58 TEST_58 N/A Test signal. Connect to an external test point.
59 TEST_59 N/A Test signal. Connect to an external test point.
60 TEST_60 Hi-Z O Test signal. Connect to an external test point.
61 UART1_nCTS Hi-Z I UART host interface
62 TEST_62 Hi-Z O Test signal. Connect to an external test point.
63 NC Hi-Z I/O Leave unconnected
64 NC Hi-Z I/O Leave unconnected
65 GND Power Ground tab used as thermal and electrical ground
(1) Using a configuration file stored on flash, the vendor can optionally block any possibility of bringing up AP using the FORCE_AP pin.