ZHCSEJ6G october   2015  – april 2023 BQ27426

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Supply Current
    6. 6.6  Digital Input and Output DC Characteristics
    7. 6.7  LDO Regulator, Wake-up, and Auto-Shutdown DC Characteristics
    8. 6.8  LDO Regulator, Wake-up, and Auto-Shutdown AC Characteristics
    9. 6.9  ADC (Temperature and Cell Measurement) Characteristics
    10. 6.10 Integrating ADC (Coulomb Counter) Characteristics
    11. 6.11 I2C-Compatible Interface Communication Timing Characteristics
    12. 6.12 SHUTDOWN and WAKE-UP Timing
    13. 6.13 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Communications
        1. 7.3.1.1 I2C Interface
        2. 7.3.1.2 I2C Time Out
        3. 7.3.1.3 I2C Command Waiting Time
        4. 7.3.1.4 I2C Clock Stretching
    4. 7.4 Device Functional Modes
      1. 7.4.1 SHUTDOWN Mode
      2. 7.4.2 POR and INITIALIZATION Modes
      3. 7.4.3 CONFIG UPDATE Mode
      4. 7.4.4 NORMAL Mode
      5. 7.4.5 SLEEP Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 BAT Voltage Sense Input
        2. 8.2.2.2 Integrated LDO Capacitor
        3. 8.2.2.3 Sense Resistor Selection
      3. 8.2.3 External Thermistor Support
      4. 8.2.4 Application Curves
  10. 9 Power Supply Recommendation
    1. 9.1 Power Supply Decoupling
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 第三方产品免责声明
      2. 11.1.2 Related Documentation
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表
  13. 12Mechanical, Packaging, and Orderable Information

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6.11 I2C-Compatible Interface Communication Timing Characteristics

TA = –40°C to 85°C; typical values at TA = 30°C and VREGIN = 3.6 V (unless otherwise noted)(1)
MIN NOM MAX UNIT
Standard Mode (100 kHz)
td(STA) Start to first falling edge of SCL 4 μs
tw(L) SCL pulse duration (low) 4.7 μs
tw(H) SCL pulse duration (high) 4 μs
tsu(STA) Setup for repeated start 4.7 μs
tsu(DAT) Data setup time Host drives SDA 250 ns
th(DAT) Data hold time Host drives SDA 0 ns
tsu(STOP) Setup time for stop 4 μs
t(BUF) Bus free time between stop and start Includes Command Waiting Time 66 μs
tf SCL or SDA fall time(1) 300 ns
tr SCL or SDA rise time(1) 300 ns
fSCL Clock frequency(2) 100 kHz
Fast Mode (400 kHz)
td(STA) Start to first falling edge of SCL 600 ns
tw(L) SCL pulse duration (low) 1300 ns
tw(H) SCL pulse duration (high) 600 ns
tsu(STA) Setup for repeated start 600 ns
tsu(DAT) Data setup time Host drives SDA 100 ns
th(DAT) Data hold time Host drives SDA 0 ns
tsu(STOP) Setup time for stop 600 ns
t(BUF) Bus free time between stop and start Includes Command Waiting Time 66 μs
tf SCL or SDA fall time(1) 300 ns
tr SCL or SDA rise time(1) 300 ns
fSCL Clock frequency(2) 400 kHz
(1) Specified by design. Not production tested.
(2) If the clock frequency (fSCL) is > 100 kHz, use 1-byte write commands for proper operation. All other transactions types are supported at 400 kHz. (See Section 7.3.1.1 and Section 7.3.1.3.)
GUID-E27A4819-0C45-4349-A5C6-7B73D5B72E08-low.gif Figure 6-1 I2C-Compatible Interface Timing Diagrams