ZHCSO21 may   2021 BQ25720

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Description (continued)
  7. 6 Device Comparison Table
  8. 7 Pin Configuration and Functions
  9. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Power-Up Sequence
      2. 9.3.2  Vmin Active Protection (VAP) with Battery only
      3. 9.3.3  Two-Level Battery Discharge Current Limit
      4. 9.3.4  Fast Role Swap Feature
      5. 9.3.5  CHRG_OK Indicator
      6. 9.3.6  Input and Charge Current Sensing
      7. 9.3.7  Input Voltage and Current Limit Setup
      8. 9.3.8  Battery Cell Configuration
      9. 9.3.9  Device HIZ State
      10. 9.3.10 USB On-The-Go (OTG)
      11. 9.3.11 Converter Operation
      12. 9.3.12 Inductance Detection Through IADPT Pin
      13. 9.3.13 Converter Compensation
      14. 9.3.14 Continuous Conduction Mode (CCM)
      15. 9.3.15 Pulse Frequency Modulation (PFM)
      16. 9.3.16 Switching Frequency and Dithering Feature
      17. 9.3.17 Current and Power Monitor
        1. 9.3.17.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)
        2. 9.3.17.2 High-Accuracy Power Sense Amplifier (PSYS)
      18. 9.3.18 Input Source Dynamic Power Management
      19. 9.3.19 Input Current Optimizer (ICO)
      20. 9.3.20 Two-Level Adapter Current Limit (Peak Power Mode)
      21. 9.3.21 Processor Hot Indication
        1. 9.3.21.1 PROCHOT During Low Power Mode
        2. 9.3.21.2 PROCHOT Status
      22. 9.3.22 Device Protection
        1. 9.3.22.1 Watchdog Timer
        2. 9.3.22.2 Input Overvoltage Protection (ACOV)
        3. 9.3.22.3 Input Overcurrent Protection (ACOC)
        4. 9.3.22.4 System Overvoltage Protection (SYSOVP)
        5. 9.3.22.5 Battery Overvoltage Protection (BATOVP)
        6. 9.3.22.6 Battery Discharge Overcurrent Protection (BATOC)
        7. 9.3.22.7 Battery Short Protection (BATSP)
        8. 9.3.22.8 System Undervoltage Lockout (VSYS_UVP) and Hiccup Mode
        9. 9.3.22.9 Thermal Shutdown (TSHUT)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Forward Mode
        1. 9.4.1.1 System Voltage Regulation with Narrow VDC Architecture
        2. 9.4.1.2 Battery Charging
      2. 9.4.2 USB On-The-Go
      3. 9.4.3 Pass Through Mode (PTM)-Patented Technology
    5. 9.5 Programming
      1. 9.5.1 SMBus Interface
        1. 9.5.1.1 SMBus Write-Word and Read-Word Protocols
        2. 9.5.1.2 Timing Diagrams
    6. 9.6 Register Map
      1. 9.6.1  ChargeOption0 Register (SMBus address = 12h) [reset = E70Eh]
      2. 9.6.2  ChargeCurrent Register (SMBus address = 14h) [reset = 0000h]
        1. 9.6.2.1 Battery Pre-Charge Current Clamp
      3. 9.6.3  ChargeVoltage Register (SMBus address = 15h) [reset value based on CELL_BATPRESZ pin setting]
      4. 9.6.4  ChargerStatus Register (SMBus address = 20h) [reset = 0000h]
      5. 9.6.5  ProchotStatus Register (SMBus address = 21h) [reset = B800h]
      6. 9.6.6  IIN_DPM Register With 10-mΩ Sense Resistor (SMBus address = 22h) [reset = 4100h]
      7. 9.6.7  ADCVBUS/PSYS Register (SMBus address = 23h)
      8. 9.6.8  ADCIBAT Register (SMBus address = 24h)
      9. 9.6.9  ADCIINCMPIN Register (SMBus address = 25h)
      10. 9.6.10 ADCVSYSVBAT Register (SMBus address = 26h)
      11. 9.6.11 ChargeOption1 Register (SMBus address = 30h) [reset = 3300h]
      12. 9.6.12 ChargeOption2 Register (SMBus address = 31h) [reset = 00B7]
      13. 9.6.13 ChargeOption3 Register (SMBus address = 32h) [reset = 0434h]
      14. 9.6.14 ProchotOption0 Register (SMBus address = 33h) [reset = 4A81h(2S~) 4A09(1S)]
      15. 9.6.15 ProchotOption1 Register (SMBus address = 34h) [reset = 41A0h]
      16. 9.6.16 ADCOption Register (SMBus address = 35h) [reset = 2000h]
      17. 9.6.17 ChargeOption4 Register (SMBus address = 36h) [reset = 0048h]
      18. 9.6.18 Vmin Active Protection Register (SMBus address = 37h) [reset = 006Ch(2s~4s)/0004h(1s)]
      19. 9.6.19 OTGVoltage Register (SMBus address = 3Bh) [reset = 09C4h]
      20. 9.6.20 OTGCurrent Register (SMBus address = 3Ch) [reset = 3C00h]
      21. 9.6.21 InputVoltage (VINDPM) Register (SMBus address = 3Dh) [reset = VBUS-1.28V]
      22. 9.6.22 VSYS_MIN Register (SMBus address = 3Eh) [reset value based on CELL_BATPRESZ pin setting]
      23. 9.6.23 IIN_HOST Register (SMBus address = 3Fh) [reset = 4100h]
      24. 9.6.24 ID Registers
        1. 9.6.24.1 ManufactureID Register (SMBus address = FEh) [reset = 0040h]
        2. 9.6.24.2 Device ID (DeviceAddress) Register (SMBus address = FFh) [reset = 00E1h]
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 ACP-ACN Input Filter
        2. 10.2.2.2 Inductor Selection
        3. 10.2.2.3 Input Capacitor
        4. 10.2.2.4 Output Capacitor
        5. 10.2.2.5 Power MOSFETs Selection
      3. 10.2.3 Application Curves
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
      1. 12.2.1 Layout Example Reference Top View
      2. 12.2.2 Inner Layer Layout and Routing Example
  14. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 第三方产品免责声明
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 接收文档更新通知
    4. 13.4 支持资源
    5. 13.5 Trademarks
    6. 13.6 静电放电警告
    7. 13.7 术语表
  15. 14Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

9.6.23 IIN_HOST Register (SMBus address = 3Fh) [reset = 4100h]

To set the nominal input current limit based on the adapter rated current. Write a 7-bit IIN_HOST register command using the data format listed in Figure 9-30, and Table 9-50.

When using a 10-mΩ sense resistor (RSNS_RAC=0b), the charger provides a nominal input-current limit range of 50 mA to 6350 mA, with 50-mA resolution. The upper boundary is implemented through DAC clamp, writing value higher than limitation will be neglected. The lower boundary is implemented through 50mA offset at code 0. Note this offset is only applied to code 0, not applied to other codes. The default nominal input current limit is 3.25 A. Upon adapter removal, the input current limit is reset to the default value of 3.25 A.

When using a 5-mΩ sense resistor (RSNS_RAC=1b) referring to Section 9.3.6, the input-current limit range can be found under certain IADPT pin, EN_FAST_5MOHM bit status. The lower boundary is implemented through 100-mA offset at code 0. Note this offset is only applied to code 0, not applied to other codes. The default current limit is 3.2 A. Due to the USB current setting requirement, the register setting specifies the maximum current instead of the typical current. Upon adapter removal, the nominal input current limit is reset to the default value of 3.2 A.

To set the maximum input current limit based on adapter rated current. Additional 100mA(10-mΩ sense resistor)/200mA(5-mΩ sense resistor) offset should be added based on above nominal input current limit to obtain the maximum input current limit.

The ACP and ACN pins are used to sense RAC with the default value of 10 mΩ.

Instead of using the internal IIN_DPM loop, the user can build up an external input current regulation loop and have the control signal on the ILIM_HIZ pin.

In order to disable ILIM_HIZ pin, the host can write to 0x31[7] to disable ILIM_HIZ pin, or pull ILIM_HIZ pin above 4.0 V.

Figure 9-30 IIN_HOST Register With 10-mΩ Sense Resistor (SMBus address = 3Fh) [reset = 4100h]
15 14 13 12 11 10 9 8
Reserved Input Current set by host, bit 6 Input Current set by host, bit 5 Input Current set by host, bit 4 Input Current set by host, bit 3 Input Current set by host, bit 2 Input Current set by host, bit 1 Input Current set by host, bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
7 6 5 4 3 2 1 0
Reserved
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-50 IIN_HOST Register With 10-mΩ Sense Resistor (SMBus address = 3Fh) Field Descriptions
SMBus
BIT		 FIELD TYPE RESET DESCRIPTION
15 Reserved R/W 0b

Not used. 1 = invalid write.
14 Input Current set by host, bit 6 R/W 1b

0 = Adds 0 mA of input current.

1 = Adds 3200 mA of input current.
13 Input Current set by host, bit 5 R/W 0b

0 = Adds 0 mA of input current.

1 = Adds 1600 mA of input current.
12 Input Current set by host, bit 4 R/W 0b

0 = Adds 0 mA of input current.

1 = Adds 800 mA of input current.
11 Input Current set by host, bit 3 R/W 0b

0 = Adds 0 mA of input current.

1 = Adds 400 mA of input current.
10 Input Current set by host, bit 2 R/W 0b

0 = Adds 0 mA of input current.

1 = Adds 200 mA of input current.
9 Input Current set by host, bit 1 R/W 0b

0 = Adds 0 mA of input current.

1 = Adds 100 mA of input current.
8 Input Current set by host, bit 0 R/W 1b

0 = Adds 0 mA of input current.

1 = Adds 50 mA of input current.
Table 9-51 IIN_HOST Register With 10-mΩ Sense Resistor (SMBus address = 3Fh) Field Descriptions
SMBus
BIT		 FIELD TYPE RESET DESCRIPTION
7-0 Reserved R 00000000b

Not used. Value Ignored.