8.5.1.48 TS_FASTCHGCTRL Register (Address = 0x61) [reset = 0x34]
TS_FASTCHGCTRL is shown in Figure 75 and described in Table 57.
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Figure 75. TS_FASTCHGCTRL Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
RESERVED |
TS_VBAT_REG__2:0 |
RESERVED |
TS_ICHRG_2:0 |
R/W-1b0 |
R/W-3b011 |
R/W-1b0 |
R/W-3b100 |
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Table 57. TS_FASTCHGCTRL Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7 |
RESERVED |
R/W |
1b0 |
Reserved |
6-4 |
TS_VBAT_REG__2:0 |
R/W |
3b011 |
Reduced target battery voltage during Warm
3b000 = No reduction
3b001 = VBAT_REG - 50mV
3b010 = VBAT_REG - 100mV
3b011 = VBAT_REG - 150mV
3b100 = VBAT_REG - 200mV
3b101 = VBAT_REG - 250mV
3b110 = VBAT_REG - 300mV
3b111 = VBAT_REG - 350mV
|
3 |
RESERVED |
R/W |
1b0 |
Reserved |
2-0 |
TS_ICHRG_2:0 |
R/W |
3b100 |
Fast charge current when decreased by TS function
3b000 = No reduction
3b001 = 0.875 x ICHG
3b010 = 0.750 x ICHG
3b011 = 0.625 x ICHG
3b100 = 0.500 x ICHG
3b101 = 0.375 x ICHG
3b110 = 0.250 x ICHG
3b111 = 0.125 x ICHG
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