SPRSP52A December   2019  – April 2020 AM6526 , AM6528 , AM6546 , AM6548

ADVANCE INFORMATION for pre-production products; subject to change without notice.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  ADC
        1. 4.3.1.1 MCU Domain
      2. 4.3.2  CAL
        1. 4.3.2.1 MAIN Domain
      3. 4.3.3  CPSW2G
        1. 4.3.3.1 MCU Domain
      4. 4.3.4  DDRSS
        1. 4.3.4.1 MAIN Domain
        2. 4.3.4.2 DDRSS Mapping
      5. 4.3.5  DMTIMER
        1. 4.3.5.1 MAIN Domain
        2. 4.3.5.2 MCU Domain
      6. 4.3.6  DSS
        1. 4.3.6.1 MAIN Domain
      7. 4.3.7  ECAP
        1. 4.3.7.1 MAIN Domain
      8. 4.3.8  EHRPWM
        1. 4.3.8.1 MAIN Domain
      9. 4.3.9  EQEP
        1. 4.3.9.1 MAIN Domain
      10. 4.3.10 GPIO
        1. 4.3.10.1 MAIN Domain
        2. 4.3.10.2 WKUP Domain
      11. 4.3.11 GPMC
        1. 4.3.11.1 MAIN Domain
      12. 4.3.12 HyperBus
        1. 4.3.12.1 MCU Domain
      13. 4.3.13 I2C
        1. 4.3.13.1 MAIN Domain
        2. 4.3.13.2 MCU Domain
        3. 4.3.13.3 WKUP Domain
      14. 4.3.14 MCAN
        1. 4.3.14.1 MCU Domain
      15. 4.3.15 MCASP
        1. 4.3.15.1 MAIN Domain
      16. 4.3.16 MCSPI
        1. 4.3.16.1 MAIN Domain
        2. 4.3.16.2 MCU Domain
      17. 4.3.17 MMCSD
        1. 4.3.17.1 MAIN Domain
      18. 4.3.18 CPTS
        1. 4.3.18.1 MAIN Domain
      19. 4.3.19 OLDI
        1. 4.3.19.1 MAIN Domain
      20. 4.3.20 OSPI
        1. 4.3.20.1 MCU Domain
      21. 4.3.21 PRU_ICSSG
        1. 4.3.21.1 MAIN Domain
      22. 4.3.22 SERDES
        1. 4.3.22.1 MAIN Domain
      23. 4.3.23 UART
        1. 4.3.23.1 MAIN Domain
        2. 4.3.23.2 MCU Domain
        3. 4.3.23.3 WKUP Domain
      24. 4.3.24 USB
        1. 4.3.24.1 MAIN Domain
      25. 4.3.25 Emulation and Debug
        1. 4.3.25.1 MAIN Domain
      26. 4.3.26 System and Miscellaneous
        1. 4.3.26.1 Boot Mode Configuration
          1. 4.3.26.1.1 MAIN Domain
          2. 4.3.26.1.2 MCU Domain
        2. 4.3.26.2 Clock
          1. 4.3.26.2.1 MAIN Domain
          2. 4.3.26.2.2 WKUP Domain
        3. 4.3.26.3 System
          1. 4.3.26.3.1 MAIN Domain
          2. 4.3.26.3.2 WKUP Domain
        4. 4.3.26.4 Miscellaneous
          1. 4.3.26.4.1 WKUP Domain
        5. 4.3.26.5 EFUSE
          1. 4.3.26.5.1 MAIN Domain
          2. 4.3.26.5.2 MCU Domain
      27. 4.3.27 Power Supply
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power-On Hours (POH)
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Operating Performance Points
      1. 5.5.1 Voltage and Core Clock Specifications
    6. 5.6 Electrical Characteristics
      1. Table 5-5  I2C OPEN DRAIN DC Electrical Characteristics
      2. Table 5-6  Analog OSC Buffers DC Electrical Characteristics
      3. Table 5-7  Analog ADC DC Electrical Characteristics
      4. Table 5-8  DPHY CSI2 Buffers DC Electrical Characteristics
      5. Table 5-9  OLDI LVDS Buffers DC Electrical Characteristics
      6. Table 5-10 LVCMOS Buffers DC Electrical Characteristics
      7. Table 5-11 LVCMOS Buffers (Reset) DC Electrical Characteristics
      8. Table 5-12 LVCMOS-FS Buffers DC Electrical Characteristics
      9. 5.6.1      USBHS Buffers DC Electrical Characteristics
      10. 5.6.2      SERDES Buffers DC Electrical Characteristics
    7. 5.7 VPP Specifications for One-Time Programmable (OTP) eFuses
      1. Table 5-13 Recommended Operating Conditions for OTP eFuse Programming
      2. 5.7.1      Hardware Requirements
      3. 5.7.2      Programming Sequence
      4. 5.7.3      Impact to Your Hardware Warranty
    8. 5.8 Thermal Resistance Characteristics
      1. Table 5-14 Thermal Resistance Characteristics
    9. 5.9 Timing and Switching Characteristics
      1. 5.9.1 Timing Parameters and Information
      2. 5.9.2 Power Supply Sequencing
        1. 5.9.2.1 Power Supply Slew Rate Requirement
        2. 5.9.2.2 VDDA_1P8_SERDES0 Supply Slew Rate Requirement
        3. 5.9.2.3 Power-Up Sequencing
        4. 5.9.2.4 Power-Down Sequencing
      3. 5.9.3 Reset Timing
        1. 5.9.3.1 Reset Electrical Data/Timing
      4. 5.9.4 Clock Specifications
        1. 5.9.4.1 Input Clocks / Oscillators
          1. 5.9.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
          2. 5.9.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
          3. 5.9.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source
          4. 5.9.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
          5. 5.9.4.1.5 Auxiliary OSC1 Not Used
          6. 5.9.4.1.6 WKUP_LFOSC0 Internal Oscillator Clock Source
          7. 5.9.4.1.7 WKUP_LFOSC0 LVCMOS Digital Clock Source
          8. 5.9.4.1.8 WKUP_LFOSC0 Not Used
        2. 5.9.4.2 Output Clocks
        3. 5.9.4.3 PLLs
        4. 5.9.4.4 Recommended Clock and Control Signal Transition Behavior
        5. 5.9.4.5 Module and Peripheral Clock Frequencies
      5. 5.9.5 Peripherals
        1. 5.9.5.1  VIN
        2. 5.9.5.2  CPSW2G
          1. 5.9.5.2.1 CPSW2G MDIO Interface Timings
          2. 5.9.5.2.2 CPSW2G RMII Timings
            1. Table 5-33 Timing Requirements for RMII[x]_REFCLK - RMII Mode
            2. Table 5-34 Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER - RMII Mode
            3. Table 5-35 Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN - RMII Mode
          3. 5.9.5.2.3 CPSW2G RGMII Timings
            1. Table 5-36 Timing Requirements for RGMII[x]_RCLK - RGMII Mode
            2. Table 5-37 Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL - RGMII Mode
            3. Table 5-38 Switching Characteristics for RGMII[x]_TCLK - RGMII Mode
            4. Table 5-39 Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL - RGMII Mode
        3. 5.9.5.3  CSI2
        4. 5.9.5.4  DDRSS
        5. 5.9.5.5  DSS
        6. 5.9.5.6  eCAP
          1. Table 5-43 Timing Requirements for eCAP
          2. Table 5-44 Switching Characteristics for eCAP
        7. 5.9.5.7  eHRPWM
          1. Table 5-45 Timing Requirements for eHRPWM
          2. Table 5-46 Switching Characteristics for eHRPWM
        8. 5.9.5.8  eQEP
          1. Table 5-47 Timing Requirements for eQEP
          2. Table 5-48 Switching Characteristics for eQEP
        9. 5.9.5.9  GPIO
          1. Table 5-49 GPIO Timing Requirements
          2. Table 5-50 GPIO Switching Characteristics
        10. 5.9.5.10 GPMC
          1. 5.9.5.10.1 GPMC and NOR Flash—Synchronous Mode
            1. Table 5-51 GPMC and NOR Flash Timing Requirements—Synchronous Mode
            2. Table 5-52 GPMC and NOR Flash Switching Characteristics—Synchronous Mode
          2. 5.9.5.10.2 GPMC and NOR Flash—Asynchronous Mode
            1. Table 5-53 GPMC and NOR Flash Timing Requirements—Asynchronous Mode
            2. Table 5-54 GPMC and NOR Flash Switching Characteristics—Asynchronous Mode
          3. 5.9.5.10.3 GPMC and NAND Flash—Asynchronous Mode
            1. Table 5-55 GPMC and NAND Flash Timing Requirements—Asynchronous Mode
            2. Table 5-56 GPMC and NAND Flash Switching Characteristics—Asynchronous Mode
        11. 5.9.5.11 HyperBus
          1. Table 5-57 Timing Requirements for HyperBus Initialization
          2. Table 5-58 HyperBus 166 MHz Switching Characteristics
          3. Table 5-59 HyperBus 100 MHz Switching Characteristics
        12. 5.9.5.12 I2C
          1. Table 5-60 Timing Requirements for I2C Input Timings
          2. Table 5-61 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        13. 5.9.5.13 MCAN
        14. 5.9.5.14 MCASP
          1. Table 5-63 Timing Requirements for MCASP
        15. 5.9.5.15 MCSPI
          1. 5.9.5.15.1 SPI—Master Mode
            1. Table 5-65 Timing Requirements for SPI - Master Mode
          2. 5.9.5.15.2 MCSPI—Slave Mode
            1. Table 5-66 Timing Requirements for SPI - Slave Mode
        16. 5.9.5.16 eMMC/SD/SDIO
          1. 5.9.5.16.1 MMCi — eMMC/SD/SDIO Card Interface
            1. 5.9.5.16.1.1 Default speed Mode
            2. 5.9.5.16.1.2 High speed Mode
            3. 5.9.5.16.1.3 UHS-I SDR12 Mode
            4. 5.9.5.16.1.4 UHS-I SDR25 Mode
            5. 5.9.5.16.1.5 UHS-I SDR50 Mode
            6. 5.9.5.16.1.6 UHS-I SDR104 / HS200 Mode
            7. 5.9.5.16.1.7 UHS-I DDR50 Mode
        17. 5.9.5.17 NAVSS
          1. Table 5-80 Timing Requirements for CPTS Input
          2. Table 5-81 Switching Characteristics for CPTS Output
        18. 5.9.5.18 OSPI
          1. 5.9.5.18.1 OSPI with Data Training
            1. Table 5-82 OSPI Switching Characteristics - Data Training
          2. 5.9.5.18.2 OSPI without Data Training
            1. Table 5-83 OSPI Switching Characteristics - DDR Mode
            2. Table 5-84 OSPI Switching Characteristics - SDR Mode
            3. Table 5-85 OSPI Timing Requirements - DDR Mode
            4. Table 5-86 OSPI Timing Requirements - SDR Mode
        19. 5.9.5.19 OLDI
          1. Table 5-88 OLDI Switching Characteristics
        20. 5.9.5.20 PCIE
        21. 5.9.5.21 PRU_ICSSG
          1. 5.9.5.21.1 Programmable Real-Time Unit (PRU_ICSSG PRU)
            1. 5.9.5.21.1.1 PRU_ICSSG PRU Direct Input/Output Mode Electrical Data and Timing
              1. Table 5-89 PRU_ICSSG PRU Switching Characteristics - Direct Output Mode
            2. 5.9.5.21.1.2 PRU_ICSSG PRU Parallel Capture Mode Electrical Data and Timing
              1. Table 5-90 PRU_ICSSG PRU Timing Requirements - Parallel Capture Mode
            3. 5.9.5.21.1.3 PRU_ICSSG PRU Shift Mode Electrical Data and Timing
              1. Table 5-91 PRU_ICSSG PRU Timing Requirements - Shift In Mode
              2. Table 5-92 PRU_ICSSG PRU Switching Characteristics - Shift Out Mode
            4. 5.9.5.21.1.4 PRU_ICSSG PRU Sigma Delta and Peripheral Interface Modes Electrical Data and Timing
              1. Table 5-93 PRU_ICSSG PRU Timing Requirements - Sigma Delta Mode
              2. Table 5-94 PRU_ICSSG PRU Timing Requirements - Peripheral Interface Mode
              3. Table 5-95 PRU_ICSSG PRU Switching Characteristics - Peripheral Interface Mode
          2. 5.9.5.21.2 PRU_ICSSG Pulse Width Modulation (PWM)
            1. 5.9.5.21.2.1 PRU_ICSSG PWM Electrical Data and Timing
              1. Table 5-96 PRU_ICSSG PWM Switching Characteristics
          3. 5.9.5.21.3 PRU_ICSSG Industrial Ethernet Peripheral (PRU_ICSSG IEP)
            1. 5.9.5.21.3.1 PRU_ICSSG IEP Electrical Data and Timing
              1. Table 5-97 PRU_ICSSG IEP Timing Requirements - Input Validated with SYNCx
              2. Table 5-98 PRU_ICSSG IEP Timing Requirements - Digital IOs
              3. Table 5-99 PRU_ICSSG IEP Timing Requirements - LATCHx_IN
          4. 5.9.5.21.4 PRU_ICSSG Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
            1. 5.9.5.21.4.1 PRU_ICSSG UART Electrical Data and Timing
              1. Table 5-100 PRU_ICSSG UART Timing Requirements
              2. Table 5-101 PRU_ICSSG UART Switching Characteristics
          5. 5.9.5.21.5 PRU_ICSSG Enhanced Capture Peripheral (PRU-ICSS ECAP)
            1. 5.9.5.21.5.1 PRU_ICSSG ECAP Electrical Data and Timing
              1. Table 5-102 PRU_ICSSG ECAP Timing Requirements
              2. Table 5-103 PRU_ICSSG ECAP Switching Characteristics
          6. 5.9.5.21.6 PRU_ICSSG RGMII, MII_RT, and Switch
            1. 5.9.5.21.6.1 PRU_ICSSG MDIO Electrical Data and Timing
              1. Table 5-104 PRU_ICSSG MDIO Timing Requirements – MDIO_DATA
              2. Table 5-105 PRU_ICSSG MDIO Switching Characteristics – MDIO_CLK
              3. Table 5-106 PRU_ICSSG MDIO Switching Characteristics – MDIO_DATA
            2. 5.9.5.21.6.2 PRU_ICSSG RGMII Electrical Data and Timing
              1. Table 5-107 PRU_ICSSG RGMII Timing Requirements - RGMII_RCLK
              2. Table 5-108 PRU_ICSSG RGMII Timing Requirements - RGMII_RD[3:0] and RGMII_RCTL
              3. Table 5-109 PRU_ICSSG RGMII Switching Characteristics - RGMII_TCLK
              4. Table 5-110 PRU_ICSSG RGMII Switching Characteristics - RGMII_TD[3:0] and RGMII_TX_CTL
            3. 5.9.5.21.6.3 PRU_ICSSG MII_RT Electrical Data and Timing
              1. Table 5-111 PRU_ICSSG MII_RT Timing Requirements – MII_RXCLK
              2. Table 5-112 PRU_ICSSG MII_RT Timing Requirements – MII_TXCLK
              3. Table 5-113 PRU_ICSSG MII_RT Timing Requirements – MII_RXD[3:0], MII_RXDV, and MII_RXER
              4. Table 5-114 PRU_ICSSG MII_RT Switching Characteristics – MII_TXD[3:0] and MII_TXEN
        22. 5.9.5.22 Timers
          1. Table 5-115 Timing Requirements for Timers
          2. Table 5-116 Switching Characteristics for Timers
        23. 5.9.5.23 UART
          1. Table 5-117 Timing Requirements for UART
          2. Table 5-118 Switching Characteristics Over Recommended Operating Conditions for UART
        24. 5.9.5.24 USB
      6. 5.9.6 Emulation and Debug
        1. 5.9.6.1 Debug Trace
        2. 5.9.6.2 IEEE 1149.1 Standard-Test-Access Port (JTAG)
          1. 5.9.6.2.1 JTAG Electrical Data and Timing
            1. Table 5-120 Timing Requirements for IEEE 1149.1 JTAG
            2. Table 5-121 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Processor Subsystems
      1. 6.2.1 Arm Cortex-A53
      2. 6.2.2 Arm Cortex-R5F
    3. 6.3 Accelerators and Coprocessors
      1. 6.3.1 PRU_ICSSG
        1. 6.3.1.1 PRU_ICSSG PRU and RTU_PRU Cores
        2. 6.3.1.2 PRU_ICSSG Broadside Accelerators Overview
        3. 6.3.1.3 PRU_ICSSG UART Module
        4. 6.3.1.4 PRU_ICSSG ECAP Module
        5. 6.3.1.5 PRU_ICSSG PWM Module
        6. 6.3.1.6 PRU_ICSSG MII_G_RT Module
        7. 6.3.1.7 PRU_ICSSG MII MDIO Module
        8. 6.3.1.8 PRU_ICSSG IEP
      2. 6.3.2 GPU
    4. 6.4 Other Subsystems
      1. 6.4.1 DMSC
      2. 6.4.2 MSMC
      3. 6.4.3 NAVSS
        1. 6.4.3.1 NAVSS0
        2. 6.4.3.2 MCU_NAVSS0
      4. 6.4.4 PDMA Controller
      5. 6.4.5 Peripherals
        1. 6.4.5.1  ADC
        2. 6.4.5.2  CAL
        3. 6.4.5.3  CPSW2G
        4. 6.4.5.4  DCC
        5. 6.4.5.5  DDRSS
        6. 6.4.5.6  DSS
        7. 6.4.5.7  ЕCAP
        8. 6.4.5.8  EPWM
        9. 6.4.5.9  ELM
        10. 6.4.5.10 ESM
        11. 6.4.5.11 EQEP
        12. 6.4.5.12 GPIO
        13. 6.4.5.13 GPMC
        14. 6.4.5.14 HyperBus
        15. 6.4.5.15 I2C
        16. 6.4.5.16 MCAN
        17. 6.4.5.17 MCASP
        18. 6.4.5.18 MCRC
        19. 6.4.5.19 MCSPI
        20. 6.4.5.20 MMCSD
        21. 6.4.5.21 OSPI
        22. 6.4.5.22 PCIE
        23. 6.4.5.23 SerDes
        24. 6.4.5.24 RTI
        25. 6.4.5.25 Timers
        26. 6.4.5.26 UART
        27. 6.4.5.27 USB
    5. 6.5 Identification
      1. 6.5.1 Revision Identification
      2. 6.5.2 Die Identification
      3. 6.5.3 JTAG Identification
      4. 6.5.4 ROM Code Identification
    6. 6.6 Boot Modes
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
        1. 7.1.1.1 Power Distribution Network Implementation Guidance
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG and EMU
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 Hardware Design Guide for AM65x/DRA80xM Devices
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 DDR Board Design and Layout Guidelines
      2. 7.2.2 OSPI Board Design and Layout Guidelines
        1. 7.2.2.1 No Loopback & Internal Pad Loopback
        2. 7.2.2.2 External Board Loopback
        3. 7.2.2.3 DQS (only available in Octal Flash devices)
      3. 7.2.3 USB Design Guidelines
      4. 7.2.4 High Speed Differential Signal Routing Guidance
      5. 7.2.5 System Power Supply Monitor Design Guidelines
      6. 7.2.6 MMC Design Guidelines
      7. 7.2.7 Integrated Power Management Features
      8. 7.2.8 External Capacitors
        1. 7.2.8.1 LVCMOS External Capacitor Connections
      9. 7.2.9 Thermal Solution Guidance
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Related Links
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ACD|784
散热焊盘机械数据 (封装 | 引脚)
订购信息

Pin Multiplexing

Table 4-75 describes the device pin multiplexing associated with pins.

NOTE

Many device pins support multiple signal functions. Some signal functions are selected via a single layer of multiplexers associated with pins. Other signal functions are selected via two or more layers of multiplexers, where one layer is associated with the pins and other layers are associated with peripheral logic functions.

Table 4-75, Pin Multiplexing only describes signal multiplexing at the pins. For more information, related to signal multiplexing at the pins, see section Pad Configuration Registers in the device TRM. Refer to the respective peripheral chapter in the device TRM for information associated with peripheral signal multiplexing.

NOTE

When a pad is set into a pin multiplexing mode which is not defined, that pad’s behavior is undefined. This should be avoided.

NOTE

Table 4-75, Pin Multiplexing does not include SerDes signal functions. For more information, see section Serializer/Deserializer (SerDes) in the device TRM.

NOTE

The PRU_ICSSG contains a second layer of multiplexing to enable additional functionality on the PRU GPO and GPI signals. This internal wrapper multiplexing is described in the PRU_ICSSG chapter in the device TRM.

For more information on the I/O cell configurations, see section Pad Configuration Registers in the device TRM.

Table 4-75 Pin Multiplexing

ADDRESS REGISTER NAME BALL NUMBER MUXMODE[7:0] SETTINGS
0 1 2 3 4 5 6 7 Bootstrap
0x0011C000 CTRLMMR_PADCONFIG0 M27 GPMC0_AD0 VOUT1_DATA0 VIN0_DATA12 GPIO0_0 BOOTMODE00
0x0011C004 CTRLMMR_PADCONFIG1 M23 GPMC0_AD1 VOUT1_DATA1 VIN0_DATA13 GPIO0_1 BOOTMODE01
0x0011C008 CTRLMMR_PADCONFIG2 M28 GPMC0_AD2 VOUT1_DATA2 VIN0_DATA14 GPIO0_2 BOOTMODE02
0x0011C00C CTRLMMR_PADCONFIG3 M24 GPMC0_AD3 VOUT1_DATA3 VIN0_DATA15 GPIO0_3 BOOTMODE03
0x0011C010 CTRLMMR_PADCONFIG4 N24 GPMC0_AD4 VOUT1_DATA4 GPIO0_4 BOOTMODE04
0x0011C014 CTRLMMR_PADCONFIG5 N27 GPMC0_AD5 VOUT1_DATA5 GPIO0_5 BOOTMODE05
0x0011C018 CTRLMMR_PADCONFIG6 N28 GPMC0_AD6 VOUT1_DATA6 GPIO0_6 BOOTMODE06
0x0011C01C CTRLMMR_PADCONFIG7 M25 GPMC0_AD7 VOUT1_DATA7 GPIO0_7 BOOTMODE07
0x0011C020 CTRLMMR_PADCONFIG8 N23 GPMC0_AD8 VOUT1_DATA8 VIN0_DATA0 PRG2_PRU0_GPO12 PRG2_PRU0_GPI12 PRG2_PWM2_A0 GPIO0_8 BOOTMODE08
0x0011C024 CTRLMMR_PADCONFIG9 M26 GPMC0_AD9 VOUT1_DATA9 VIN0_DATA1 PRG2_PRU0_GPO13 PRG2_PRU0_GPI13 PRG2_PWM2_B0 GPIO0_9 BOOTMODE09
0x0011C028 CTRLMMR_PADCONFIG10 P28 GPMC0_AD10 VOUT1_DATA10 VIN0_DATA2 PRG2_PRU0_GPO14 PRG2_PRU0_GPI14 PRG2_PWM0_TZ_IN GPIO0_10 BOOTMODE10
0x0011C02C CTRLMMR_PADCONFIG11 P27 GPMC0_AD11 VOUT1_DATA11 VIN0_DATA3 PRG2_PRU0_GPO15 PRG2_PRU0_GPI15 PRG2_PWM2_A1 GPIO0_11 BOOTMODE11
0x0011C030 CTRLMMR_PADCONFIG12 N26 GPMC0_AD12 VOUT1_DATA12 VIN0_DATA4 PRG2_PRU1_GPO12 PRG2_PRU1_GPI12 PRG2_PWM2_B1 GPIO0_12 BOOTMODE12
0x0011C034 CTRLMMR_PADCONFIG13 N25 GPMC0_AD13 VOUT1_DATA13 VIN0_DATA5 PRG2_PRU1_GPO13 PRG2_PRU1_GPI13 PRG2_PWM2_A2 GPIO0_13 BOOTMODE13
0x0011C038 CTRLMMR_PADCONFIG14 P24 GPMC0_AD14 VOUT1_DATA14 VIN0_DATA6 PRG2_PRU1_GPO14 PRG2_PRU1_GPI14 PRG2_PWM0_TZ_OUT GPIO0_14 BOOTMODE14
0x0011C03C CTRLMMR_PADCONFIG15 R27 GPMC0_AD15 VOUT1_DATA15 VIN0_DATA7 PRG2_PRU1_GPO15 PRG2_PRU1_GPI15 PRG2_PWM2_B2 GPIO0_15 BOOTMODE15
0x0011C040 CTRLMMR_PADCONFIG16 R28 GPMC0_CLK VOUT1_DATA16 VIN0_PCLK GPMC0_FCLK_MUX GPIO0_16
0x0011C044 CTRLMMR_PADCONFIG17 P25 GPMC0_ADVn_ALE VOUT1_DATA17 GPIO0_17 BOOTMODE16
0x0011C048 CTRLMMR_PADCONFIG18 P26 GPMC0_OEn_REn VOUT1_DATA18 GPIO0_18 BOOTMODE17
0x0011C04C CTRLMMR_PADCONFIG19 U28 GPMC0_WEn VOUT1_DATA19 GPIO0_19 BOOTMODE18
0x0011C050 CTRLMMR_PADCONFIG20 T28 GPMC0_BE0n_CLE VOUT1_DATA20 GPIO0_20
0x0011C054 CTRLMMR_PADCONFIG21 P23 GPMC0_BE1n VOUT1_DATA21 VIN0_HD PRG2_PRU0_GPO17 PRG2_PRU0_GPI17 TIMER_IO2 PRG2_PWM2_TZ_IN GPIO0_21
0x0011C058 CTRLMMR_PADCONFIG22 R26 GPMC0_WAIT0 VOUT1_DATA22 GPIO0_22
0x0011C05C CTRLMMR_PADCONFIG23 R23 GPMC0_WAIT1 VOUT1_DATA23 VIN0_VD PRG2_PWM1_A0 PRG2_IEP1_EDC_LATCH_IN0 TIMER_IO3 PRG2_IEP0_EDIO_DATA_IN_OUT28 GPIO0_23
0x0011C060 CTRLMMR_PADCONFIG24 T25 GPMC0_WPn VOUT1_VSYNC GPIO0_24
0x0011C064 CTRLMMR_PADCONFIG25 T24 GPMC0_DIR VOUT1_HSYNC VIN0_DATA8 PRG2_PWM1_B0 PRG2_IEP1_EDC_SYNC_OUT0 TIMER_IO6 PRG2_IEP0_EDIO_DATA_IN_OUT29 GPIO0_25
0x0011C068 CTRLMMR_PADCONFIG26 R24 GPMC0_CSn0 VOUT1_PCLK GPIO0_26
0x0011C06C CTRLMMR_PADCONFIG27 T23 GPMC0_CSn1 VOUT1_DE VIN0_DATA9 PRG2_PRU1_GPO17 PRG2_PRU1_GPI17 TIMER_IO7 PRG2_PWM2_TZ_OUT GPIO0_27
0x0011C070 CTRLMMR_PADCONFIG28 R25 GPMC0_CSn2 VOUT1_EXTPCLKIN VIN0_DATA10 GPMC0_A27 PRG2_IEP1_EDC_LATCH_IN1 I2C2_SDA PRG2_IEP0_EDIO_DATA_IN_OUT30 GPIO0_28
0x0011C074 CTRLMMR_PADCONFIG29 T27 GPMC0_CSn3 VIN0_DATA11 GPMC0_A26 PRG2_IEP1_EDC_SYNC_OUT1 I2C2_SCL PRG2_IEP0_EDIO_DATA_IN_OUT31 GPIO0_29
0x0011C078 CTRLMMR_PADCONFIG30 AF18 PRG2_PRU0_GPO0 PRG2_PRU0_GPI0 PRG2_RGMII1_RD0 GPMC0_A25 TRC_CLK EHRPWM0_SYNCI PRG2_PWM3_A0 GPIO0_30
0x0011C07C CTRLMMR_PADCONFIG31 AE18 PRG2_PRU0_GPO1 PRG2_PRU0_GPI1 PRG2_RGMII1_RD1 GPMC0_A24 TRC_CTL EHRPWM0_SYNCO SYNC2_OUT GPIO0_31
0x0011C080 CTRLMMR_PADCONFIG32 AH17 PRG2_PRU0_GPO2 PRG2_PRU0_GPI2 PRG2_RGMII1_RD2 GPMC0_A23 TRC_DATA0 EHRPWM_TZn_IN0 SYNC3_OUT GPIO0_32
0x0011C084 CTRLMMR_PADCONFIG33 AG18 PRG2_PRU0_GPO3 PRG2_PRU0_GPI3 PRG2_RGMII1_RD3 GPMC0_A22 TRC_DATA1 EHRPWM0_A PRG2_PWM3_B0 GPIO0_33
0x0011C088 CTRLMMR_PADCONFIG34 AG17 PRG2_PRU0_GPO4 PRG2_PRU0_GPI4 PRG2_RGMII1_RX_CTL GPMC0_A21 TRC_DATA2 EHRPWM0_B PRG2_PWM0_A0 GPIO0_34
0x0011C08C CTRLMMR_PADCONFIG35 AF17 PRG2_PRU0_GPO5 PRG2_PRU0_GPI5 PRG2_RGMII1_RXC GPMC0_A20 TRC_DATA3 EHRPWM1_A PRG2_PWM3_A1 GPIO0_35
0x0011C090 CTRLMMR_PADCONFIG36 AE17 PRG2_PRU0_GPO6 PRG2_PRU0_GPI6 PRG2_RGMII1_TX_CTL GPMC0_A19 TRC_DATA4 EHRPWM1_B PRG2_PWM3_B1 GPIO0_36
0x0011C094 CTRLMMR_PADCONFIG37 AC19 PRG2_PRU0_GPO7 PRG2_PRU0_GPI7 PRG2_MDIO0_MDIO GPMC0_A18 TRC_DATA5 EHRPWM_TZn_IN1 EHRPWM_SOCA GPIO0_37
0x0011C098 CTRLMMR_PADCONFIG38 AH16 PRG2_PRU0_GPO8 PRG2_PRU0_GPI8 PRG2_RGMII1_TD0 GPMC0_A17 TRC_DATA6 EHRPWM2_A PRG2_PWM0_B0 GPIO0_38
0x0011C09C CTRLMMR_PADCONFIG39 AG16 PRG2_PRU0_GPO9 PRG2_PRU0_GPI9 PRG2_RGMII1_TD1 GPMC0_A16 TRC_DATA7 EHRPWM2_B GPIO0_39
0x0011C0A0 CTRLMMR_PADCONFIG40 AF16 PRG2_PRU0_GPO10 PRG2_PRU0_GPI10 PRG2_RGMII1_TD2 GPMC0_A15 TRC_DATA8 EHRPWM_TZn_IN2 EHRPWM_SOCB GPIO0_40
0x0011C0A4 CTRLMMR_PADCONFIG41 AE16 PRG2_PRU0_GPO11 PRG2_PRU0_GPI11 PRG2_RGMII1_TD3 GPMC0_A14 TRC_DATA9 PRG2_ECAP0_IN_APWM_OUT GPIO0_41
0x0011C0A8 CTRLMMR_PADCONFIG42 AD16 PRG2_PRU0_GPO16 PRG2_PRU0_GPI16 PRG2_RGMII1_TXC GPMC0_A13 TRC_DATA10 PRG2_PWM0_A1 GPIO0_42
0x0011C0AC CTRLMMR_PADCONFIG43 AH15 PRG2_PRU1_GPO0 PRG2_PRU1_GPI0 PRG2_RGMII2_RD0 GPMC0_A12 TRC_DATA11 EHRPWM3_A PRG2_PWM3_A2 GPIO0_43
0x0011C0B0 CTRLMMR_PADCONFIG44 AC16 PRG2_PRU1_GPO1 PRG2_PRU1_GPI1 PRG2_RGMII2_RD1 GPMC0_A11 TRC_DATA12 EHRPWM3_B PRG2_PWM3_B2 GPIO0_44
0x0011C0B4 CTRLMMR_PADCONFIG45 AD17 PRG2_PRU1_GPO2 PRG2_PRU1_GPI2 PRG2_RGMII2_RD2 GPMC0_A10 TRC_DATA13 EHRPWM3_SYNCI PRG2_PWM0_B1 GPIO0_45
0x0011C0B8 CTRLMMR_PADCONFIG46 AH14 PRG2_PRU1_GPO3 PRG2_PRU1_GPI3 PRG2_RGMII2_RD3 GPMC0_A9 TRC_DATA14 EHRPWM3_SYNCO GPIO0_46
0x0011C0BC CTRLMMR_PADCONFIG47 AG14 PRG2_PRU1_GPO4 PRG2_PRU1_GPI4 PRG2_RGMII2_RX_CTL GPMC0_A8 TRC_DATA15 EHRPWM_TZn_IN3 PRG2_ECAP0_SYNC_OUT GPIO0_47
0x0011C0C0 CTRLMMR_PADCONFIG48 AG15 PRG2_PRU1_GPO5 PRG2_PRU1_GPI5 PRG2_RGMII2_RXC GPMC0_A7 TRC_DATA16 EHRPWM4_A GPIO0_48
0x0011C0C4 CTRLMMR_PADCONFIG49 AC17 PRG2_PRU1_GPO6 PRG2_PRU1_GPI6 PRG2_RGMII2_TX_CTL GPMC0_A6 TRC_DATA17 EHRPWM4_B GPIO0_49
0x0011C0C8 CTRLMMR_PADCONFIG50 AE15 PRG2_PRU1_GPO7 PRG2_PRU1_GPI7 PRG2_MDIO0_MDC GPMC0_A5 TRC_DATA18 EHRPWM_TZn_IN4 PRG2_PWM3_TZ_IN GPIO0_50
0x0011C0CC CTRLMMR_PADCONFIG51 AD15 PRG2_PRU1_GPO8 PRG2_PRU1_GPI8 PRG2_RGMII2_TD0 GPMC0_A4 TRC_DATA19 EHRPWM5_A PRG2_PWM0_A2 GPIO0_51
0x0011C0D0 CTRLMMR_PADCONFIG52 AF14 PRG2_PRU1_GPO9 PRG2_PRU1_GPI9 PRG2_RGMII2_TD1 GPMC0_A3 TRC_DATA20 EHRPWM5_B PRG2_PWM3_TZ_OUT GPIO0_52
0x0011C0D4 CTRLMMR_PADCONFIG53 AC15 PRG2_PRU1_GPO10 PRG2_PRU1_GPI10 PRG2_RGMII2_TD2 GPMC0_A2 TRC_DATA21 EHRPWM_TZn_IN5 PRG2_PWM0_B2 GPIO0_53
0x0011C0D8 CTRLMMR_PADCONFIG54 AD14 PRG2_PRU1_GPO11 PRG2_PRU1_GPI11 PRG2_RGMII2_TD3 GPMC0_A1 TRC_DATA22 PRG2_ECAP0_SYNC_IN GPIO0_54
0x0011C0DC CTRLMMR_PADCONFIG55 AE14 PRG2_PRU1_GPO16 PRG2_PRU1_GPI16 PRG2_RGMII2_TXC GPMC0_A0 TRC_DATA23 PRG2_PWM1_TZ_OUT GPIO0_55
0x0011C0E0 CTRLMMR_PADCONFIG56 AE22 PRG1_PRU0_GPO0 PRG1_PRU0_GPI0 PRG1_RGMII1_RD0 PRG1_PWM3_A0 GPIO0_56
0x0011C0E4 CTRLMMR_PADCONFIG57 AG24 PRG1_PRU0_GPO1 PRG1_PRU0_GPI1 PRG1_RGMII1_RD1 PRG1_PWM3_B0 GPIO0_57
0x0011C0E8 CTRLMMR_PADCONFIG58 AF23 PRG1_PRU0_GPO2 PRG1_PRU0_GPI2 PRG1_RGMII1_RD2 PRG1_PWM2_A0 GPIO0_58
0x0011C0EC CTRLMMR_PADCONFIG59 AD21 PRG1_PRU0_GPO3 PRG1_PRU0_GPI3 PRG1_RGMII1_RD3 PRG1_PWM3_A2 GPIO0_59
0x0011C0F0 CTRLMMR_PADCONFIG60 AG23 PRG1_PRU0_GPO4 PRG1_PRU0_GPI4 PRG1_RGMII1_RX_CTL PRG1_PWM2_B0 GPIO0_60
0x0011C0F4 CTRLMMR_PADCONFIG61 AF27 PRG1_PRU0_GPO5 PRG1_PRU0_GPI5 PRG1_PWM3_B2 GPIO0_61
0x0011C0F8 CTRLMMR_PADCONFIG62 AF22 PRG1_PRU0_GPO6 PRG1_PRU0_GPI6 PRG1_RGMII1_RXC PRG1_PWM3_A1 GPIO0_62
0x0011C0FC CTRLMMR_PADCONFIG63 AG27 PRG1_PRU0_GPO7 PRG1_PRU0_GPI7 PRG1_IEP0_EDC_LATCH_IN1 PRG1_PWM3_B1 GPIO0_63
0x0011C100 CTRLMMR_PADCONFIG64 AF28 PRG1_PRU0_GPO8 PRG1_PRU0_GPI8 PRG1_PWM2_A1 GPIO0_64
0x0011C104 CTRLMMR_PADCONFIG65 AF26 PRG1_PRU0_GPO9 PRG1_PRU0_GPI9 PRG1_UART0_CTSn PRG1_PWM3_TZ_IN SPI2_CS1 PRG1_IEP0_EDIO_DATA_IN_OUT28 GPIO0_65
0x0011C108 CTRLMMR_PADCONFIG66 AH25 PRG1_PRU0_GPO10 PRG1_PRU0_GPI10 PRG1_UART0_RTSn PRG1_PWM2_B1 SPI2_CS2 PRG1_IEP0_EDIO_DATA_IN_OUT29 GPIO0_66
0x0011C10C CTRLMMR_PADCONFIG67 AF21 PRG1_PRU0_GPO11 PRG1_PRU0_GPI11 PRG1_RGMII1_TX_CTL PRG1_PWM3_TZ_OUT PRG1_PRU0_GPO15 GPIO0_67
0x0011C110 CTRLMMR_PADCONFIG68 AH20 PRG1_PRU0_GPO12 PRG1_PRU0_GPI12 PRG1_RGMII1_TD0 PRG1_PWM0_A0 PRG1_PRU0_GPO11 GPIO0_68
0x0011C114 CTRLMMR_PADCONFIG69 AH21 PRG1_PRU0_GPO13 PRG1_PRU0_GPI13 PRG1_RGMII1_TD1 PRG1_PWM0_B0 PRG1_PRU0_GPO12 GPIO0_69
0x0011C118 CTRLMMR_PADCONFIG70 AG20 PRG1_PRU0_GPO14 PRG1_PRU0_GPI14 PRG1_RGMII1_TD2 PRG1_PWM0_A1 PRG1_PRU0_GPO13 GPIO0_70
0x0011C11C CTRLMMR_PADCONFIG71 AD19 PRG1_PRU0_GPO15 PRG1_PRU0_GPI15 PRG1_RGMII1_TD3 PRG1_PWM0_B1 PRG1_PRU0_GPO14 GPIO0_71
0x0011C120 CTRLMMR_PADCONFIG72 AD20 PRG1_PRU0_GPO16 PRG1_PRU0_GPI16 PRG1_RGMII1_TXC PRG1_PWM0_A2 GPIO0_72
0x0011C124 CTRLMMR_PADCONFIG73 AH26 PRG1_PRU0_GPO17 PRG1_PRU0_GPI17 PRG1_IEP0_EDC_SYNC_OUT1 PRG1_PWM0_B2 GPIO0_73
0x0011C128 CTRLMMR_PADCONFIG74 AG25 PRG1_PRU0_GPO18 PRG1_PRU0_GPI18 PRG1_IEP0_EDC_LATCH_IN0 PRG1_PWM0_TZ_IN GPIO0_74
0x0011C12C CTRLMMR_PADCONFIG75 AG26 PRG1_PRU0_GPO19 PRG1_PRU0_GPI19 PRG1_IEP0_EDC_SYNC_OUT0 PRG1_PWM0_TZ_OUT GPIO0_75
0x0011C130 CTRLMMR_PADCONFIG76 AH24 PRG1_PRU1_GPO0 PRG1_PRU1_GPI0 PRG1_RGMII2_RD0 GPIO0_76
0x0011C134 CTRLMMR_PADCONFIG77 AH23 PRG1_PRU1_GPO1 PRG1_PRU1_GPI1 PRG1_RGMII2_RD1 GPIO0_77
0x0011C138 CTRLMMR_PADCONFIG78 AG21 PRG1_PRU1_GPO2 PRG1_PRU1_GPI2 PRG1_RGMII2_RD2 PRG1_PWM2_A2 GPIO0_78
0x0011C13C CTRLMMR_PADCONFIG79 AH22 PRG1_PRU1_GPO3 PRG1_PRU1_GPI3 PRG1_RGMII2_RD3 EQEP1_A GPIO0_79
0x0011C140 CTRLMMR_PADCONFIG80 AE21 PRG1_PRU1_GPO4 PRG1_PRU1_GPI4 PRG1_RGMII2_RX_CTL PRG1_PWM2_B2 EQEP1_B GPIO0_80
0x0011C144 CTRLMMR_PADCONFIG81 AC22 PRG1_PRU1_GPO5 PRG1_PRU1_GPI5 EQEP1_S GPIO0_81
0x0011C148 CTRLMMR_PADCONFIG82 AG22 PRG1_PRU1_GPO6 PRG1_PRU1_GPI6 PRG1_RGMII2_RXC GPIO0_82
0x0011C14C CTRLMMR_PADCONFIG83 AD23 PRG1_PRU1_GPO7 PRG1_PRU1_GPI7 PRG1_IEP1_EDC_LATCH_IN1 SPI2_CS0 UART1_TXD GPIO0_83
0x0011C150 CTRLMMR_PADCONFIG84 AE24 PRG1_PRU1_GPO8 PRG1_PRU1_GPI8 PRG1_PWM2_TZ_OUT GPIO0_84
0x0011C154 CTRLMMR_PADCONFIG85 AF25 PRG1_PRU1_GPO9 PRG1_PRU1_GPI9 PRG1_UART0_RXD PRG1_IEP0_EDIO_DATA_IN_OUT30 GPIO0_85
0x0011C158 CTRLMMR_PADCONFIG86 AF24 PRG1_PRU1_GPO10 PRG1_PRU1_GPI10 PRG1_UART0_TXD PRG1_PWM2_TZ_IN SPI2_CS3 PRG1_IEP0_EDIO_DATA_IN_OUT31 GPIO0_86
0x0011C15C CTRLMMR_PADCONFIG87 AC20 PRG1_PRU1_GPO11 PRG1_PRU1_GPI11 PRG1_RGMII2_TX_CTL EQEP1_I PRG1_PRU1_GPO15 GPIO0_87
0x0011C160 CTRLMMR_PADCONFIG88 AE20 PRG1_PRU1_GPO12 PRG1_PRU1_GPI12 PRG1_RGMII2_TD0 PRG1_PWM1_A0 PRG1_PRU1_GPO11 GPIO0_88
0x0011C164 CTRLMMR_PADCONFIG89 AF19 PRG1_PRU1_GPO13 PRG1_PRU1_GPI13 PRG1_RGMII2_TD1 PRG1_PWM1_B0 PRG1_PRU1_GPO12 GPIO0_89
0x0011C168 CTRLMMR_PADCONFIG90 AH19 PRG1_PRU1_GPO14 PRG1_PRU1_GPI14 PRG1_RGMII2_TD2 PRG1_PWM1_A1 PRG1_PRU1_GPO13 GPIO0_90
0x0011C16C CTRLMMR_PADCONFIG91 AG19 PRG1_PRU1_GPO15 PRG1_PRU1_GPI15 PRG1_RGMII2_TD3 PRG1_PWM1_B1 PRG1_PRU1_GPO14 GPIO0_91
0x0011C170 CTRLMMR_PADCONFIG92 AE19 PRG1_PRU1_GPO16 PRG1_PRU1_GPI16 PRG1_RGMII2_TXC PRG1_PWM1_A2 GPIO0_92
0x0011C174 CTRLMMR_PADCONFIG93 AE23 PRG1_PRU1_GPO17 PRG1_PRU1_GPI17 PRG1_IEP1_EDC_SYNC_OUT1 PRG1_PWM1_B2 SPI2_CLK PRG1_ECAP0_SYNC_OUT UART1_RXD GPIO0_93
0x0011C178 CTRLMMR_PADCONFIG94 AD22 PRG1_PRU1_GPO18 PRG1_PRU1_GPI18 PRG1_IEP1_EDC_LATCH_IN0 PRG1_PWM1_TZ_IN SPI2_D0 PRG1_ECAP0_SYNC_IN UART1_CTSn GPIO0_94
0x0011C17C CTRLMMR_PADCONFIG95 AC21 PRG1_PRU1_GPO19 PRG1_PRU1_GPI19 PRG1_IEP1_EDC_SYNC_OUT0 PRG1_PWM1_TZ_OUT SPI2_D1 PRG1_ECAP0_IN_APWM_OUT UART1_RTSn GPIO0_95
0x0011C180 CTRLMMR_PADCONFIG96 AD18 PRG1_MDIO0_MDIO SPI1_CS2 PRG2_PWM1_A1 GPIO1_0
0x0011C184 CTRLMMR_PADCONFIG97 AH18 PRG1_MDIO0_MDC SPI1_CS3 PRG2_PWM1_B1 GPIO1_1
0x0011C188 CTRLMMR_PADCONFIG98 D25 MMC0_DAT7 UART0_DCDn EQEP2_A GPIO1_2
0x0011C18C CTRLMMR_PADCONFIG99 B26 MMC0_DAT6 UART0_DSRn EQEP2_B GPIO1_3
0x0011C190 CTRLMMR_PADCONFIG100 A24 MMC0_DAT5 UART0_DTRn EQEP2_I GPIO1_4
0x0011C194 CTRLMMR_PADCONFIG101 E24 MMC0_DAT4 UART0_RIN EQEP2_S GPIO1_5
0x0011C198 CTRLMMR_PADCONFIG102 A25 MMC0_DAT3 GPIO1_6
0x0011C19C CTRLMMR_PADCONFIG103 C26 MMC0_DAT2 GPIO1_7
0x0011C1A0 CTRLMMR_PADCONFIG104 E25 MMC0_DAT1 GPIO1_8
0x0011C1A4 CTRLMMR_PADCONFIG105 A26 MMC0_DAT0 GPIO1_9
0x0011C1A8 CTRLMMR_PADCONFIG106 B25 MMC0_CLK GPIO1_10
0x0011C1AC CTRLMMR_PADCONFIG107 B27 MMC0_CMD GPIO1_11
0x0011C1B0 CTRLMMR_PADCONFIG108 C25 MMC0_DS GPIO1_12
0x0011C1B4 CTRLMMR_PADCONFIG109 A23 MMC0_SDCD PRG2_IEP0_EDIO_OUTVALID GPIO1_13
0x0011C1B8 CTRLMMR_PADCONFIG110 B23 MMC0_SDWP GPIO1_14
0x0011C1BC CTRLMMR_PADCONFIG111 AG13 SPI0_CS0 GPIO1_15
0x0011C1C0 CTRLMMR_PADCONFIG112 AF13 SPI0_CS1 CPTS0_TS_COMP I2C3_SCL PRG1_IEP0_EDIO_OUTVALID GPIO1_16
0x0011C1C4 CTRLMMR_PADCONFIG113 AH13 SPI0_CLK GPIO1_17
0x0011C1C8 CTRLMMR_PADCONFIG114 AE13 SPI0_D0 GPIO1_18
0x0011C1CC CTRLMMR_PADCONFIG115 AD13 SPI0_D1 GPIO1_19
0x0011C1D0 CTRLMMR_PADCONFIG116 AD12 SPI1_CS0 PRG2_IEP0_EDC_LATCH_IN0 PRG2_UART0_CTSn PRG0_IEP0_EDIO_OUTVALID GPIO1_20
0x0011C1D4 CTRLMMR_PADCONFIG117 AG12 SPI1_CS1 CPTS0_TS_SYNC I2C3_SDA GPIO1_21
0x0011C1D8 CTRLMMR_PADCONFIG118 AH12 SPI1_CLK PRG2_IEP0_EDC_SYNC_OUT0 PRG2_UART0_RTSn GPIO1_22
0x0011C1DC CTRLMMR_PADCONFIG119 AE12 SPI1_D0 PRG2_IEP0_EDC_LATCH_IN1 PRG2_UART0_RXD GPIO1_23
0x0011C1E0 CTRLMMR_PADCONFIG120 AF12 SPI1_D1 PRG2_IEP0_EDC_SYNC_OUT1 PRG2_UART0_TXD GPIO1_24
0x0011C1E4 CTRLMMR_PADCONFIG121 AF11 UART0_RXD GPIO1_25
0x0011C1E8 CTRLMMR_PADCONFIG122 AE11 UART0_TXD GPIO1_26
0x0011C1EC CTRLMMR_PADCONFIG123 AG11 UART0_CTSn TIMER_IO4 SPI0_CS2 GPIO1_27
0x0011C1F0 CTRLMMR_PADCONFIG124 AD11 UART0_RTSn TIMER_IO5 SPI0_CS3 GPIO1_28
0x0011C1F4 CTRLMMR_PADCONFIG125 V24 PRG0_PRU0_GPO0 PRG0_PRU0_GPI0 PRG0_RGMII1_RD0 PRG0_PWM3_A0 MCASP0_ACLKX GPIO1_29
0x0011C1F8 CTRLMMR_PADCONFIG126 W25 PRG0_PRU0_GPO1 PRG0_PRU0_GPI1 PRG0_RGMII1_RD1 PRG0_PWM3_B0 MCASP0_AFSX GPIO1_30
0x0011C1FC CTRLMMR_PADCONFIG127 W24 PRG0_PRU0_GPO2 PRG0_PRU0_GPI2 PRG0_RGMII1_RD2 PRG0_PWM2_A0 MCASP0_ACLKR GPIO1_31
0x0011C200 CTRLMMR_PADCONFIG128 AA27 PRG0_PRU0_GPO3 PRG0_PRU0_GPI3 PRG0_RGMII1_RD3 PRG0_PWM3_A2 MCASP0_AFSR GPIO1_32
0x0011C204 CTRLMMR_PADCONFIG129 Y24 PRG0_PRU0_GPO4 PRG0_PRU0_GPI4 PRG0_RGMII1_RX_CTL PRG0_PWM2_B0 MCASP0_AXR0 GPIO1_33
0x0011C208 CTRLMMR_PADCONFIG130 V28 PRG0_PRU0_GPO5 PRG0_PRU0_GPI5 PRG0_PWM3_B2 MCASP0_AXR1 GPIO1_34
0x0011C20C CTRLMMR_PADCONFIG131 Y25 PRG0_PRU0_GPO6 PRG0_PRU0_GPI6 PRG0_RGMII1_RXC PRG0_PWM3_A1 MCASP0_AXR2 GPIO1_35
0x0011C210 CTRLMMR_PADCONFIG132 U27 PRG0_PRU0_GPO7 PRG0_PRU0_GPI7 PRG0_IEP0_EDC_LATCH_IN1 PRG0_PWM3_B1 PRG0_ECAP0_SYNC_IN MCASP0_AXR3 GPIO1_36
0x0011C214 CTRLMMR_PADCONFIG133 V27 PRG0_PRU0_GPO8 PRG0_PRU0_GPI8 PRG0_PWM2_A1 MCASP0_AXR4 GPIO1_37
0x0011C218 CTRLMMR_PADCONFIG134 V26 PRG0_PRU0_GPO9 PRG0_PRU0_GPI9 PRG0_UART0_CTSn PRG0_PWM3_TZ_IN SPI3_CS1 MCASP0_AXR5 PRG0_IEP0_EDIO_DATA_IN_OUT28 GPIO1_38
0x0011C21C CTRLMMR_PADCONFIG135 U25 PRG0_PRU0_GPO10 PRG0_PRU0_GPI10 PRG0_UART0_RTSn PRG0_PWM2_B1 SPI3_CS2 MCASP0_AXR6 PRG0_IEP0_EDIO_DATA_IN_OUT29 GPIO1_39
0x0011C220 CTRLMMR_PADCONFIG136 AB25 PRG0_PRU0_GPO11 PRG0_PRU0_GPI11 PRG0_RGMII1_TX_CTL PRG0_PWM3_TZ_OUT PRG0_PRU0_GPO15 MCASP0_AXR7 GPIO1_40
0x0011C224 CTRLMMR_PADCONFIG137 AD27 PRG0_PRU0_GPO12 PRG0_PRU0_GPI12 PRG0_RGMII1_TD0 PRG0_PWM0_A0 PRG0_PRU0_GPO11 MCASP0_AXR8 GPIO1_41
0x0011C228 CTRLMMR_PADCONFIG138 AC26 PRG0_PRU0_GPO13 PRG0_PRU0_GPI13 PRG0_RGMII1_TD1 PRG0_PWM0_B0 PRG0_PRU0_GPO12 MCASP0_AXR9 GPIO1_42
0x0011C22C CTRLMMR_PADCONFIG139 AD26 PRG0_PRU0_GPO14 PRG0_PRU0_GPI14 PRG0_RGMII1_TD2 PRG0_PWM0_A1 PRG0_PRU0_GPO13 MCASP0_AXR10 GPIO1_43
0x0011C230 CTRLMMR_PADCONFIG140 AA24 PRG0_PRU0_GPO15 PRG0_PRU0_GPI15 PRG0_RGMII1_TD3 PRG0_PWM0_B1 PRG0_PRU0_GPO14 MCASP0_AXR11 GPIO1_44
0x0011C234 CTRLMMR_PADCONFIG141 AD28 PRG0_PRU0_GPO16 PRG0_PRU0_GPI16 PRG0_RGMII1_TXC PRG0_PWM0_A2 MCASP0_AXR12 MCASP1_AHCLKR GPIO1_45
0x0011C238 CTRLMMR_PADCONFIG142 U26 PRG0_PRU0_GPO17 PRG0_PRU0_GPI17 PRG0_IEP0_EDC_SYNC_OUT1 PRG0_PWM0_B2 PRG0_ECAP0_SYNC_OUT MCASP0_AXR13 MCASP1_AHCLKX GPIO1_46
0x0011C23C CTRLMMR_PADCONFIG143 V25 PRG0_PRU0_GPO18 PRG0_PRU0_GPI18 PRG0_IEP0_EDC_LATCH_IN0 PRG0_PWM0_TZ_IN PRG0_ECAP0_IN_APWM_OUT MCASP0_AXR14 MCASP2_AHCLKR GPIO1_47
0x0011C240 CTRLMMR_PADCONFIG144 U24 PRG0_PRU0_GPO19 PRG0_PRU0_GPI19 PRG0_IEP0_EDC_SYNC_OUT0 PRG0_PWM0_TZ_OUT MCASP0_AXR15 MCASP2_AHCLKX GPIO1_48
0x0011C244 CTRLMMR_PADCONFIG145 AB28 PRG0_PRU1_GPO0 PRG0_PRU1_GPI0 PRG0_RGMII2_RD0 MCASP1_ACLKX GPIO1_49
0x0011C248 CTRLMMR_PADCONFIG146 AC28 PRG0_PRU1_GPO1 PRG0_PRU1_GPI1 PRG0_RGMII2_RD1 MCASP1_AFSX GPIO1_50
0x0011C24C CTRLMMR_PADCONFIG147 AC27 PRG0_PRU1_GPO2 PRG0_PRU1_GPI2 PRG0_RGMII2_RD2 PRG0_PWM2_A2 MCASP1_ACLKR GPIO1_51
0x0011C250 CTRLMMR_PADCONFIG148 AB26 PRG0_PRU1_GPO3 PRG0_PRU1_GPI3 PRG0_RGMII2_RD3 EQEP0_A MCASP1_AFSR GPIO1_52
0x0011C254 CTRLMMR_PADCONFIG149 AA25 PRG0_PRU1_GPO4 PRG0_PRU1_GPI4 PRG0_RGMII2_RX_CTL PRG0_PWM2_B2 EQEP0_B MCASP1_AXR0 MCASP0_AHCLKR GPIO1_53
0x0011C258 CTRLMMR_PADCONFIG150 U23 PRG0_PRU1_GPO5 PRG0_PRU1_GPI5 EQEP0_S MCASP1_AXR1 MCASP0_AHCLKX GPIO1_54
0x0011C25C CTRLMMR_PADCONFIG151 AB27 PRG0_PRU1_GPO6 PRG0_PRU1_GPI6 PRG0_RGMII2_RXC MCASP1_AXR2 GPIO1_55
0x0011C260 CTRLMMR_PADCONFIG152 W28 PRG0_PRU1_GPO7 PRG0_PRU1_GPI7 PRG0_IEP1_EDC_LATCH_IN1 SPI3_CS0 MCASP1_AXR3 UART2_TXD GPIO1_56
0x0011C264 CTRLMMR_PADCONFIG153 W27 PRG0_PRU1_GPO8 PRG0_PRU1_GPI8 PRG0_PWM2_TZ_OUT MCASP1_AXR4 GPIO1_57
0x0011C268 CTRLMMR_PADCONFIG154 Y28 PRG0_PRU1_GPO9 PRG0_PRU1_GPI9 PRG0_UART0_RXD SPI3_CS3 MCASP1_AXR5 PRG0_IEP0_EDIO_DATA_IN_OUT30 GPIO1_58
0x0011C26C CTRLMMR_PADCONFIG155 AA28 PRG0_PRU1_GPO10 PRG0_PRU1_GPI10 PRG0_UART0_TXD PRG0_PWM2_TZ_IN EQEP0_I MCASP1_AXR6 PRG0_IEP0_EDIO_DATA_IN_OUT31 GPIO1_59
0x0011C270 CTRLMMR_PADCONFIG156 AB24 PRG0_PRU1_GPO11 PRG0_PRU1_GPI11 PRG0_RGMII2_TX_CTL PRG0_PRU1_GPO15 MCASP1_AXR7 GPIO1_60
0x0011C274 CTRLMMR_PADCONFIG157 AC25 PRG0_PRU1_GPO12 PRG0_PRU1_GPI12 PRG0_RGMII2_TD0 PRG0_PWM1_A0 PRG0_PRU1_GPO11 MCASP1_AXR8 GPIO1_61
0x0011C278 CTRLMMR_PADCONFIG158 AD25 PRG0_PRU1_GPO13 PRG0_PRU1_GPI13 PRG0_RGMII2_TD1 PRG0_PWM1_B0 PRG0_PRU1_GPO12 MCASP1_AXR9 GPIO1_62
0x0011C27C CTRLMMR_PADCONFIG159 AD24 PRG0_PRU1_GPO14 PRG0_PRU1_GPI14 PRG0_RGMII2_TD2 PRG0_PWM1_A1 PRG0_PRU1_GPO13 MCASP2_AFSR GPIO1_63
0x0011C280 CTRLMMR_PADCONFIG160 AE27 PRG0_PRU1_GPO15 PRG0_PRU1_GPI15 PRG0_RGMII2_TD3 PRG0_PWM1_B1 PRG0_PRU1_GPO14 MCASP2_ACLKR GPIO1_64
0x0011C284 CTRLMMR_PADCONFIG161 AC24 PRG0_PRU1_GPO16 PRG0_PRU1_GPI16 PRG0_RGMII2_TXC PRG0_PWM1_A2 MCASP2_AXR0 GPIO1_65
0x0011C288 CTRLMMR_PADCONFIG162 Y27 PRG0_PRU1_GPO17 PRG0_PRU1_GPI17 PRG0_IEP1_EDC_SYNC_OUT1 PRG0_PWM1_B2 SPI3_CLK MCASP2_AXR1 UART2_RXD GPIO1_66
0x0011C28C CTRLMMR_PADCONFIG163 Y26 PRG0_PRU1_GPO18 PRG0_PRU1_GPI18 PRG0_IEP1_EDC_LATCH_IN0 PRG0_PWM1_TZ_IN SPI3_D0 MCASP2_AFSX UART2_CTSn GPIO1_67
0x0011C290 CTRLMMR_PADCONFIG164 W26 PRG0_PRU1_GPO19 PRG0_PRU1_GPI19 PRG0_IEP1_EDC_SYNC_OUT0 PRG0_PWM1_TZ_OUT SPI3_D1 MCASP2_ACLKX UART2_RTSn GPIO1_68
0x0011C294 CTRLMMR_PADCONFIG165 AE26 PRG0_MDIO0_MDIO PRG2_PWM1_A2 MCASP2_AXR2 GPIO1_69
0x0011C298 CTRLMMR_PADCONFIG166 AE28 PRG0_MDIO0_MDC PRG2_PWM1_B2 MCASP2_AXR3 GPIO1_70
0x0011C29C CTRLMMR_PADCONFIG167 F18 NMIn PRG2_PWM1_TZ_IN
0x0011C2A0 CTRLMMR_PADCONFIG168 F17 RESETz
0x0011C2A4 CTRLMMR_PADCONFIG169 D19 RESETSTATz
0x0011C2A8 CTRLMMR_PADCONFIG170 C19 PORz_OUT
0x0011C2AC CTRLMMR_PADCONFIG171 E20 SOC_SAFETY_ERRORn
0x0011C2B0 CTRLMMR_PADCONFIG172 C20 TDI
0x0011C2B4 CTRLMMR_PADCONFIG173 A20 TDO
0x0011C2B8 CTRLMMR_PADCONFIG174 A21 TMS
0x0011C2BC CTRLMMR_PADCONFIG175 AD9 USB0_DRVVBUS GPIO1_71
0x0011C2C0 CTRLMMR_PADCONFIG176 AC8 USB1_DRVVBUS GPIO1_72
0x0011C2C4 CTRLMMR_PADCONFIG177 D27 MMC1_DAT3 GPIO1_73
0x0011C2C8 CTRLMMR_PADCONFIG178 D26 MMC1_DAT2 GPIO1_74
0x0011C2CC CTRLMMR_PADCONFIG179 E27 MMC1_DAT1 GPIO1_75
0x0011C2D0 CTRLMMR_PADCONFIG180 D28 MMC1_DAT0 GPIO1_76
0x0011C2D4 CTRLMMR_PADCONFIG181 C27 MMC1_CLK GPIO1_77
0x0011C2D8 CTRLMMR_PADCONFIG182 C28 MMC1_CMD GPIO1_78
0x0011C2DC CTRLMMR_PADCONFIG183 B24 MMC1_SDCD GPIO1_79
0x0011C2E0 CTRLMMR_PADCONFIG184 C24 MMC1_SDWP GPIO1_80
0x0011C2E8 CTRLMMR_PADCONFIG186 D20 I2C0_SCL
0x0011C2EC CTRLMMR_PADCONFIG187 C21 I2C0_SDA
0x0011C2F0 CTRLMMR_PADCONFIG188 B21 I2C1_SCL CPTS0_HW1TSPUSH
0x0011C2F4 CTRLMMR_PADCONFIG189 E21 I2C1_SDA CPTS0_HW2TSPUSH
0x0011C2F8 CTRLMMR_PADCONFIG190 D21 ECAP0_IN_APWM_OUT SYNC0_OUT CPTS0_RFT_CLK GPIO1_86
0x0011C2FC CTRLMMR_PADCONFIG191 A22 EXT_REFCLK1 SYNC1_OUT GPIO1_87
0x0011C300 CTRLMMR_PADCONFIG192 B22 TIMER_IO0 SYSCLKOUT0 GPIO1_88
0x0011C304 CTRLMMR_PADCONFIG193 C23 TIMER_IO1 OBSCLK0 GPIO1_89
0x0011C308 CTRLMMR_PADCONFIG194 E19 PORz
0x4301C000 CTRLMMR_WKUP_PADCONFIG0 V1 MCU_OSPI0_CLK MCU_HYPERBUS0_CK WKUP_GPIO0_12
0x4301C004 CTRLMMR_WKUP_PADCONFIG1 U1 MCU_OSPI0_LBCLKO MCU_HYPERBUS0_CKn WKUP_GPIO0_13
0x4301C008 CTRLMMR_WKUP_PADCONFIG2 U2 MCU_OSPI0_DQS MCU_HYPERBUS0_RWDS WKUP_GPIO0_14
0x4301C00C CTRLMMR_WKUP_PADCONFIG3 U4 MCU_OSPI0_D0 MCU_HYPERBUS0_DQ0 WKUP_GPIO0_15
0x4301C010 CTRLMMR_WKUP_PADCONFIG4 U5 MCU_OSPI0_D1 MCU_HYPERBUS0_DQ1 WKUP_GPIO0_16
0x4301C014 CTRLMMR_WKUP_PADCONFIG5 T2 MCU_OSPI0_D2 MCU_HYPERBUS0_DQ2 WKUP_GPIO0_17
0x4301C018 CTRLMMR_WKUP_PADCONFIG6 T3 MCU_OSPI0_D3 MCU_HYPERBUS0_DQ3 WKUP_GPIO0_18
0x4301C01C CTRLMMR_WKUP_PADCONFIG7 T4 MCU_OSPI0_D4 MCU_HYPERBUS0_DQ4 WKUP_GPIO0_19
0x4301C020 CTRLMMR_WKUP_PADCONFIG8 T5 MCU_OSPI0_D5 MCU_HYPERBUS0_DQ5 WKUP_GPIO0_20
0x4301C024 CTRLMMR_WKUP_PADCONFIG9 R2 MCU_OSPI0_D6 MCU_HYPERBUS0_DQ6 WKUP_GPIO0_21
0x4301C028 CTRLMMR_WKUP_PADCONFIG10 R3 MCU_OSPI0_D7 MCU_HYPERBUS0_DQ7 WKUP_GPIO0_22
0x4301C02C CTRLMMR_WKUP_PADCONFIG11 R4 MCU_OSPI0_CSn0 MCU_HYPERBUS0_CSn0 WKUP_GPIO0_23
0x4301C030 CTRLMMR_WKUP_PADCONFIG12 R5 MCU_OSPI0_CSn1 MCU_HYPERBUS0_RESETn WKUP_GPIO0_24
0x4301C034 CTRLMMR_WKUP_PADCONFIG13 T1 MCU_OSPI1_CLK WKUP_GPIO0_25
0x4301C038 CTRLMMR_WKUP_PADCONFIG14 R1 MCU_OSPI1_LBCLKO MCU_OSPI0_CSn2 MCU_HYPERBUS0_RESETOn WKUP_GPIO0_26
0x4301C03C CTRLMMR_WKUP_PADCONFIG15 P2 MCU_OSPI1_DQS MCU_OSPI0_CSn3 MCU_HYPERBUS0_INTn WKUP_GPIO0_27
0x4301C040 CTRLMMR_WKUP_PADCONFIG16 P3 MCU_OSPI1_D0 WKUP_GPIO0_28
0x4301C044 CTRLMMR_WKUP_PADCONFIG17 P4 MCU_OSPI1_D1 MCU_UART0_RXD MCU_SPI1_CS1 WKUP_GPIO0_29
0x4301C048 CTRLMMR_WKUP_PADCONFIG18 P5 MCU_OSPI1_D2 MCU_UART0_TXD MCU_SPI1_CS2 WKUP_GPIO0_30
0x4301C04C CTRLMMR_WKUP_PADCONFIG19 P1 MCU_OSPI1_D3 MCU_UART0_CTSn MCU_SPI0_CS1 WKUP_GPIO0_31
0x4301C050 CTRLMMR_WKUP_PADCONFIG20 N2 MCU_OSPI1_CSn0 WKUP_GPIO0_32
0x4301C054 CTRLMMR_WKUP_PADCONFIG21 N3 MCU_OSPI1_CSn1 MCU_HYPERBUS0_WPn MCU_TIMER_IO0 MCU_HYPERBUS0_CSn1 MCU_UART0_RTSn MCU_SPI0_CS2 WKUP_GPIO0_33
0x4301C058 CTRLMMR_WKUP_PADCONFIG22 N4 MCU_RGMII1_TX_CTL MCU_RMII1_CRS_DV WKUP_GPIO0_34
0x4301C05C CTRLMMR_WKUP_PADCONFIG23 N5 MCU_RGMII1_RX_CTL MCU_RMII1_RX_ER WKUP_GPIO0_35
0x4301C060 CTRLMMR_WKUP_PADCONFIG24 M2 MCU_RGMII1_TD3 WKUP_GPIO0_36
0x4301C064 CTRLMMR_WKUP_PADCONFIG25 M3 MCU_RGMII1_TD2 WKUP_GPIO0_37
0x4301C068 CTRLMMR_WKUP_PADCONFIG26 M4 MCU_RGMII1_TD1 MCU_RMII1_TXD1 WKUP_GPIO0_38
0x4301C06C CTRLMMR_WKUP_PADCONFIG27 M5 MCU_RGMII1_TD0 MCU_RMII1_TXD0 WKUP_GPIO0_39
0x4301C070 CTRLMMR_WKUP_PADCONFIG28 N1 MCU_RGMII1_TXC MCU_RMII1_TX_EN WKUP_GPIO0_40
0x4301C074 CTRLMMR_WKUP_PADCONFIG29 M1 MCU_RGMII1_RXC MCU_RMII1_REF_CLK WKUP_GPIO0_41
0x4301C078 CTRLMMR_WKUP_PADCONFIG30 L2 MCU_RGMII1_RD3 WKUP_GPIO0_42
0x4301C07C CTRLMMR_WKUP_PADCONFIG31 L5 MCU_RGMII1_RD2 WKUP_GPIO0_43
0x4301C080 CTRLMMR_WKUP_PADCONFIG32 M6 MCU_RGMII1_RD1 MCU_RMII1_RXD1 WKUP_GPIO0_44
0x4301C084 CTRLMMR_WKUP_PADCONFIG33 L6 MCU_RGMII1_RD0 MCU_RMII1_RXD0 WKUP_GPIO0_45
0x4301C088 CTRLMMR_WKUP_PADCONFIG34 L4 MCU_MDIO0_MDIO WKUP_GPIO0_46
0x4301C08C CTRLMMR_WKUP_PADCONFIG35 L1 MCU_MDIO0_MDC WKUP_GPIO0_47
0x4301C090 CTRLMMR_WKUP_PADCONFIG36 Y1 MCU_SPI0_CLK WKUP_GPIO0_48 MCU_BOOTMODE06
0x4301C094 CTRLMMR_WKUP_PADCONFIG37 Y3 MCU_SPI0_D0 WKUP_GPIO0_49 MCU_BOOTMODE07
0x4301C098 CTRLMMR_WKUP_PADCONFIG38 Y2 MCU_SPI0_D1 WKUP_GPIO0_50 MCU_BOOTMODE05
0x4301C09C CTRLMMR_WKUP_PADCONFIG39 Y4 MCU_SPI0_CS0 WKUP_GPIO0_51
0x4301C0A0 CTRLMMR_WKUP_PADCONFIG40 AB1 WKUP_UART0_RXD WKUP_GPIO0_52
0x4301C0A4 CTRLMMR_WKUP_PADCONFIG41 AB5 WKUP_UART0_TXD WKUP_GPIO0_53
0x4301C0A8 CTRLMMR_WKUP_PADCONFIG42 W1 MCU_MCAN0_TX WKUP_GPIO0_54
0x4301C0AC CTRLMMR_WKUP_PADCONFIG43 W2 MCU_MCAN0_RX WKUP_GPIO0_55
0x4301C0B0 CTRLMMR_WKUP_PADCONFIG44 AF4 WKUP_GPIO0_0 MCU_SPI1_CLK WKUP_GPIO0_0 MCU_BOOTMODE00
0x4301C0B4 CTRLMMR_WKUP_PADCONFIG45 AF3 WKUP_GPIO0_1 MCU_SPI1_D0 WKUP_GPIO0_1 MCU_BOOTMODE01
0x4301C0B8 CTRLMMR_WKUP_PADCONFIG46 AE3 WKUP_GPIO0_2 MCU_SPI1_D1 WKUP_GPIO0_2 MCU_BOOTMODE02
0x4301C0BC CTRLMMR_WKUP_PADCONFIG47 AD1 WKUP_GPIO0_3 MCU_SPI1_CS0 WKUP_GPIO0_3 MCU_BOOTMODE03
0x4301C0C0 CTRLMMR_WKUP_PADCONFIG48 AC3 WKUP_GPIO0_4 MCU_MCAN1_TX MCU_SPI0_CS3 MCU_ADC_EXT_TRIGGER0 WKUP_GPIO0_4 MCU_BOOTMODE04
0x4301C0C4 CTRLMMR_WKUP_PADCONFIG49 AD3 WKUP_GPIO0_5 MCU_MCAN1_RX MCU_SPI1_CS3 MCU_ADC_EXT_TRIGGER1 WKUP_GPIO0_5
0x4301C0C8 CTRLMMR_WKUP_PADCONFIG50 AC2 WKUP_GPIO0_6 WKUP_UART0_CTSn MCU_CPTS0_HW1TSPUSH WKUP_GPIO0_6
0x4301C0CC CTRLMMR_WKUP_PADCONFIG51 AC1 WKUP_GPIO0_7 WKUP_UART0_RTSn MCU_CPTS0_HW2TSPUSH WKUP_GPIO0_7
0x4301C0D0 CTRLMMR_WKUP_PADCONFIG52 AC5 WKUP_GPIO0_8 MCU_CPTS0_TS_SYNC WKUP_GPIO0_8 MCU_BOOTMODE08
0x4301C0D4 CTRLMMR_WKUP_PADCONFIG53 AB4 WKUP_GPIO0_9 MCU_CPTS0_TS_COMP WKUP_GPIO0_9 MCU_BOOTMODE09
0x4301C0D8 CTRLMMR_WKUP_PADCONFIG54 AB3 WKUP_GPIO0_10 MCU_EXT_REFCLK0 MCU_CPTS0_RFT_CLK MCU_SYSCLKOUT0 WKUP_GPIO0_10
0x4301C0DC CTRLMMR_WKUP_PADCONFIG55 AB2 WKUP_GPIO0_11 MCU_OBSCLK0 MCU_TIMER_IO1 MCU_CLKOUT0 WKUP_GPIO0_11
0x4301C0E0 CTRLMMR_WKUP_PADCONFIG56 AC7 WKUP_I2C0_SCL
0x4301C0E4 CTRLMMR_WKUP_PADCONFIG57 AD6 WKUP_I2C0_SDA
0x4301C0E8 CTRLMMR_WKUP_PADCONFIG58 AD8 MCU_I2C0_SCL
0x4301C0EC CTRLMMR_WKUP_PADCONFIG59 AD7 MCU_I2C0_SDA
0x4301C0F0 CTRLMMR_WKUP_PADCONFIG60 AA5 PMIC_POWER_EN1
0x4301C0F4 CTRLMMR_WKUP_PADCONFIG61 W3 MCU_SAFETY_ERRORn
0x4301C0F8 CTRLMMR_WKUP_PADCONFIG62 W4 MCU_RESETz
0x4301C0FC CTRLMMR_WKUP_PADCONFIG63 V3 MCU_RESETSTATz
0x4301C100 CTRLMMR_WKUP_PADCONFIG64 V2 MCU_PORz_OUT
0x4301C104 CTRLMMR_WKUP_PADCONFIG65 AA4 TCK
0x4301C108 CTRLMMR_WKUP_PADCONFIG66 AA3 TRSTn
0x4301C10C CTRLMMR_WKUP_PADCONFIG67 AA2 EMU0
0x4301C110 CTRLMMR_WKUP_PADCONFIG68 AA1 EMU1
0x4301C114 CTRLMMR_WKUP_PADCONFIG69 Y5 PMIC_POWER_EN0