ZHCSK88A September   2010  – September 2019 ADS7947 , ADS7948 , ADS7949

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     ADS794x 方框图
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions: ADS794x (12-, 10-, 8-Bit)
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: ADS7947 (12-Bit)
    6. 7.6  Electrical Characteristics: ADS7948 (10-Bit)
    7. 7.7  Electrical Characteristics: ADS7949 (8-Bit)
    8. 7.8  Timing Requirements
    9. 7.9  Switching Characteristics
    10. 7.10 Typical Characteristics: ADS7947, ADS7948, ADS7949
    11. 7.11 Typical Characteristics: ADS7947 (12-Bit)
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Multiplexer and ADC Input
      2. 8.3.2 Reference
      3. 8.3.3 Clock
      4. 8.3.4 ADC Transfer Function
      5. 8.3.5 Power-Down
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Operation
    5. 8.5 Programming
      1. 8.5.1 16-Clock Frame
      2. 8.5.2 32-Clock Frame
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Driving an ADC Without a Driving Op Amp
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 相关链接
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.5 Electrical Characteristics: ADS7947 (12-Bit)

minimum and maximum values at AVDD = 2.7 V to 5.5 V, DVDD = 1.65 V to AVDD, TA = –40°C to +125°C, and
fSAMPLE = 2 MSPS (unless otherwise noted); typical values at AVDD = 3 V, DVDD = 1.8 V, TA = +25°C, and fSAMPLE = 2 MSPS
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Input capacitance(4) 32 pF
Input leakage current At +125°C 1.5 nA
SYSTEM PERFORMANCE
Resolution 12 Bits
No missing codes 12 Bits
Integral linearity –1 ±0.3 1 LSB(1)
Differential linearity –1 ±0.3 1 LSB
Offset error(2) –1 ±0.3 1 LSB
Gain error –1 ±0.3 1 LSB
Transition noise 25 µVRMS
Power-supply rejection 60 dB
SAMPLING DYNAMICS
Conversion time 13.5 SCLK
Acquisition time 80 ns
Maximum sample rate (throughput rate) 34-MHz SCLK with a 16-clock frame 2 MSPS
34-MHz SCLK and CS low for 13.5 clocks 2.1 MSPS
Aperture delay 5 ns
Aperture jitter 10 ps
Step response 80 ns
Overvoltage recovery 80 ns
DYNAMIC CHARACTERISTICS
Total harmonic distortion (THD)(3) 100kHz –85 dB
Signal-to-noise ratio (SNR) 100 kHz 72 73 dB
Signal-to-noise and distortion ratio (SINAD) 100 kHz 72.75 dB
Spurious-free dynamic range (SFDR) 100 kHz 86 dB
Full-power bandwidth At –3 dB 15 MHz
DIGITAL INPUT/OUTPUT
Logic family CMOS
Logic level VIH 0.7DVDD V
VIL 0.3DVDD V
VOH ISOURCE = 200 µA DVDD – 0.2 V
VOL ISINK = 200 µA 0.4 V
Input leakage current IIH, IIL 0 < VIN < DVDD ±20 nA
POWER-SUPPLY REQUIREMENTS
AVDD supply current IDYNAMIC AVDD = 3.3 V, fSAMPLE = 2 MSPS 2.5 mA
AVDD = 5 V, fSAMPLE = 2 MSPS 3 3.5 mA
ISTATIC AVDD = 3.3 V, SCLK off 1.8 mA
AVDD = 5 V, SCLK off 1.9 2.5 mA
DVDD supply current(5) DVDD = 3.3 V, SCLK = 34 MHz,
SDO load 20 pF		 500 µA
Power-down state AVDD supply current IPD-DYNAMIC SCLK = 34 MHz 550 µA
IPD-STATIC SCLK off 2.5 µA
Power-up time 1 µs
(1) LSB means least significant bit.
(2) Measured relative to an ideal full-scale input.
(3) Calculated on the first nine harmonics of the input frequency.
(4) See Figure 40 for sampling circuit details.
(5) DVDD consumes only dynamic current. IDVDD = CLOAD × DVDD × number of 0→1 transitions in SDO × fSAMPLE. This current is load-dependent and there is no DVDD current when the output is not toggling.