ZHCSBL9F October   2012  – May 2016 ADS42LB49 , ADS42LB69

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: ADS42LB69 (16-Bit)
    6. 6.6  Electrical Characteristics: ADS42LB49 (14-Bit)
    7. 6.7  Electrical Characteristics: General
    8. 6.8  Digital Characteristics
    9. 6.9  Timing Requirements: General
    10. 6.10 Timing Requirements: DDR LVDS Mode
    11. 6.11 Timing Requirements: QDR LVDS Mode
    12. 6.12 Typical Characteristics: ADS42LB69
    13. 6.13 Typical Characteristics: ADS42LB49
    14. 6.14 Typical Characteristics: Common
    15. 6.15 Typical Characteristics: Contour
      1. 6.15.1 Spurious-Free Dynamic Range (SFDR): General
      2. 6.15.2 Signal-to-Noise Ratio (SNR): ADS42LB69
      3. 6.15.3 Signal-to-Noise Ratio (SNR): ADS42LB49
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Digital Gain
      2. 8.3.2 Input Clock Divider
      3. 8.3.3 Overrange Indication
        1. 8.3.3.1 OVR in a QDR Pinout
        2. 8.3.3.2 OVR in a DDR Pinout
        3. 8.3.3.3 Programming Threshold for Fast OVR
      4. 8.3.4 LVDS Buffer
      5. 8.3.5 Output Data Format
    4. 8.4 Device Functional Modes
      1. 8.4.1 Digital Output Information
        1. 8.4.1.1 Output Interface
        2. 8.4.1.2 DDR LVDS Outputs
        3. 8.4.1.3 QDR LVDS Outputs
    5. 8.5 Programming
      1. 8.5.1 Device Configuration
      2. 8.5.2 Details of Serial Interface
        1. 8.5.2.1 Register Initialization
        2. 8.5.2.2 Serial Register Write
        3. 8.5.2.3 Serial Register Readout
    6. 8.6 Register Maps
      1. 8.6.1 Description of Serial Interface Registers
        1. 8.6.1.1  Register 6 (offset = 06h) [reset = 80h]
        2. 8.6.1.2  Register 7 (offset = 07h) [reset = 00h]
        3. 8.6.1.3  Register 8 (offset = 08h) [reset = 00h]
        4. 8.6.1.4  Register B (offset = 0Bh) [reset = 00h]
        5. 8.6.1.5  Register C (offset = 0Ch) [reset = 00h]
        6. 8.6.1.6  Register D (offset = 0Dh) [reset = 6Ch]
        7. 8.6.1.7  Register F (offset = 0Fh) [reset = 00h]
        8. 8.6.1.8  Register 10 (offset = 10h) [reset = 00h]
        9. 8.6.1.9  Register 11 (offset = 11h) [reset = 00h]
        10. 8.6.1.10 Register 12 (offset = 12h) [reset = 00h]
        11. 8.6.1.11 Register 13 (offset = 13h) [reset = 00h]
        12. 8.6.1.12 Register 14 (offset = 14h) [reset = 00h]
        13. 8.6.1.13 Register 15 (offset = 15h) [reset = 00h]
        14. 8.6.1.14 Register 16 (offset = 16h) [reset = 00h]
        15. 8.6.1.15 Register 17 (offset = 17h) [reset = 00h]
        16. 8.6.1.16 Register 18 (offset = 18h) [reset = 00h]
        17. 8.6.1.17 Register 1F (offset = 1Fh) [reset = 7Fh]
        18. 8.6.1.18 Register 20 (offset = 20h) [reset = 00h]
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Analog Input
          1. 9.2.2.1.1 Drive Circuit Requirements
          2. 9.2.2.1.2 Driving Circuit
          3. 9.2.2.1.3 Using the ADS42LBx9 In Time-Domain, Low-Frequency Pulse Applications
        2. 9.2.2.2 Clock Input
        3. 9.2.2.3 SNR and Clock Jitter
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 相关链接
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

To obtain the best performance in an application, careful consideration must be given to the design of the input analog circuit and common-mode, clock circuit, and power-supply rails. The Typical Application section discusses these critical design considerations in detail.

9.2 Typical Application

Because the ADS42LBx9 is a dual-channel device, it can be used in a dual-channel superheterodyne receiver, as shown in Figure 109. In a superheterodyne receiver, the high-frequency RF signal is first mixed down to a lower Intermediate frequency (IF). The ADS42LBxx can be used in the IF stage to sample and digitize the IF signal. The digital data can be encoded either in offset binary or twos complement format and transmitted to a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC). Inside the FPGA or ASIC, the digital data are down-converted to the baseband frequency with a digital mixer and numerically controlled oscillator (NCO).

ADS42LB49 ADS42LB69 ai_2chan_heterodyne_rx_slas904.gif Figure 109. The ADS42LBx9 in a Dual-Channel Superheterodyne Receiver

9.2.1 Design Requirements

Specific design requirements are provided in Table 35.

Table 35. ADS42LBx9 Design Requirements

DESIGN PARAMETER VALUE
fSAMPLING 250 MSPS
IF 10 MHz (Figure 123), 170 MHz (Figure 124)
SNR > 72 dBc
SFDR > 80 dBc
HDn > 90 dBc

9.2.2 Detailed Design Procedure

The choice of drive circuit at the analog and clock inputs can degrade the performance of the ADC. In order to obtain the design specifications given in Table 35, the following design guidelines discussed in this section must be followed.

9.2.2.1 Analog Input

The analog input pins have analog buffers (running from the AVDD3V supply) that internally drive the differential sampling circuit. As a result of the analog buffer, the input pins present high input impedance to the external driving source (at dc, a 10-kΩ differential input resistance is provided in shunt with a 4-pF differential input capacitance). The buffer helps isolate the external driving source from the switching currents of the sampling circuit. This buffering makes driving the buffered inputs easier than when compared to an ADC without the buffer.

The input common-mode is set internally using a 5-kΩ resistor from each input pin to VCM so the input signal can be ac-coupled to the pins. Each input pin (INP, INM) must swing symmetrically between VCM + 0.5 V and VCM – 0.5 V, resulting in a 2-VPP differential input swing. When programmed for 2.5-VPP full-scale, each input pin must swing symmetrically between VCM + 0.625 V and VCM – 0.625 V.

The input sampling circuit has a high 3-dB bandwidth that extends up to 900 MHz (measured with a 50-Ω source driving a 50-Ω termination between INP and INM). The dynamic offset of the first-stage sub-ADC limits the maximum analog input frequency to approximately 250 MHz (with a 2.5-VPP full-scale amplitude) and to approximately 400 MHz (with a 2-VPP full-scale amplitude). This maximum analog input frequency is different than the analog bandwidth of 900 MHz, which is only an indicator of signal amplitude versus frequency.

9.2.2.1.1 Drive Circuit Requirements

For optimum performance, the analog inputs must be driven differentially. This technique improves the common-mode noise immunity and even-order harmonic rejection. A small resistor (10 Ω) in series with each input pin is recommended to damp out ringing caused by package parasitics.

Figure 110, Figure 111, and Figure 112 show the differential impedance (ZIN = RIN || CIN) at the ADC input pins. The presence of the analog input buffer results in an almost constant input capacitance up to 1 GHz.

ADS42LB49 ADS42LB69 adc_eqvlnt_inp_impnc_LAS900.gif
1.

NOINDENT:

X = A or B.
2.

NOINDENT:

ZIN = RIN || (1 / jωCIN).
Figure 110. ADC Equivalent Input Impedance
ADS42LB49 ADS42LB69 G073_SLAS900.png
Figure 111. ADC Analog Input Resistance (RIN) Across Frequency
ADS42LB49 ADS42LB69 G074_SLAS900.png
Figure 112. ADC Analog Input Capacitance (CIN) Across Frequency

9.2.2.1.2 Driving Circuit

An example driving circuit configuration is shown in Figure 113. To optimize even-harmonic performance at high input frequencies (greater than the first Nyquist), the use of back-to-back transformers is recommended, as shown in Figure 113. Note that the drive circuit is terminated by 50 Ω near the ADC side. The ac-coupling capacitors allow the analog inputs to self-bias around the required common-mode voltage. If HD2 optimization is a concern, using a 10-Ω series resistor on the INP side and a 9.5-Ω series resistor on the INM side may help improve HD2 by 2 dB to 3 dB at a 85-dBFS level on a 170-MHz IF. An additional R-C-R (39 Ω - 6.8 pF - 39 Ω) circuit placed near device pins helps further improve HD3.

ADS42LB49 ADS42LB69 ai_drive_cir_freq_upto250mhz_las904.gif Figure 113. Drive Circuit for Input Frequencies up to 250 MHz

The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch and good performance is obtained for high-frequency input signals. An additional termination resistor pair may be required between the two transformers, as shown in Figure 113. The center point of this termination is connected to ground to improve the balance between the P (positive) and M (negative) sides. The values of the terminations between the transformers and on the secondary side must be chosen to obtain an effective 50 Ω (for a 50-Ω source impedance). For high input frequencies (>250MHz), the R-C-R circuit can be removed as indicated in Figure 114.

ADS42LB49 ADS42LB69 ai_drive_cir_freq_morethan250mhz_las904.gif Figure 114. Drive Circuit for Input Frequencies > 250 MHz

9.2.2.1.3 Using the ADS42LBx9 In Time-Domain, Low-Frequency Pulse Applications

The analog buffers inside the device are implemented to provide excellent linearity over a wide range of frequencies. However, at very low frequencies (< 100 kHz) the buffer presents a high-pass response, as shown in Figure 115 and Figure 116. This response does not affect most frequency-domain applications, but can require compensation techniques for time-domain, dc-coupled applications. Application report SBAA220 discusses simple techniques to compensate for the analog buffer response.

ADS42LB49 ADS42LB69 Anlg_Bffr_SLAS904.gif Figure 115. Analog Buffer in the ADS42LBx9
ADS42LB49 ADS42LB69 D075_SLAS904E.gif Figure 116. Buffer Response at Very Low Input Frequencies

9.2.2.2 Clock Input

The device clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to 1.4 V using internal 5-kΩ resistors. The self-bias clock inputs of the ADS42LB69 and ADS42LB49 can be driven by the transformer-coupled, sine-wave clock source or by the ac-coupled, LVPECL and LVDS clock sources, as shown in Figure 117, Figure 118, and Figure 119. Figure 119 details the internal clock buffer.

ADS42LB49 ADS42LB69 ai_dif_sinewave_clk_bas550.gif

NOTE:

RT = termination resistor, if necessary.
Figure 117. Differential Sine-Wave Clock Driving Circuit
ADS42LB49 ADS42LB69 ai_lvds_clk_drv_bas550.gif Figure 118. LVDS Clock Driving Circuit
ADS42LB49 ADS42LB69 ai_lvpecl_clk_drv_bas550.gif Figure 119. LVPECL Clock Driving Circuit
ADS42LB49 ADS42LB69 ai_intclk_buffer_las900.gif

NOTE:

CEQ is 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer.
Figure 120. Internal Clock Buffer

A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-μF capacitor, as shown in Figure 121. However, for best performance the clock inputs must be driven differentially, thereby reducing susceptibility to common-mode noise. For high input frequency sampling, TI recommends using a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter. There is no change in performance with a non-50% duty cycle clock input.

ADS42LB49 ADS42LB69 ai_drv_cir_1end_las900.gif Figure 121. Single-Ended Clock Driving Circuit

9.2.2.3 SNR and Clock Jitter

The signal-to-noise ratio (SNR) of the ADC is limited by three different factors, as shown in Equation 3. Quantization noise is typically not noticeable in pipeline converters and is 96 dBFS for a 16-bit ADC. Thermal noise limits SNR at low input frequencies and clock jitter sets SNR for higher input frequencies.

Equation 3. ADS42LB49 ADS42LB69 Eq1_las900.gif

SNR limitation is a result of sample clock jitter and can be calculated by Equation 4:

Equation 4. ADS42LB49 ADS42LB69 Eq2_las900.gif

The total clock jitter (TJitter) has three components: the internal aperture jitter (85 fS for the device) is set by the noise of the clock input buffer, the external clock jitter, and the jitter from the analog input signal. TJitter can be calculated by Equation 5:

Equation 5. ADS42LB49 ADS42LB69 Eq3_las900.gif

External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass filters at the clock input while a faster clock slew rate improves ADC aperture jitter. The device has a 74.1-dBFS thermal noise and an 85-fS internal aperture jitter. The SNR value depends on the amount of external jitter for different input frequencies, as shown in Figure 122.

ADS42LB49 ADS42LB69 AI_G2_las900.gif Figure 122. SNR versus Input Frequency and External Clock Jitter

9.2.3 Application Curves

ADS42LB49 ADS42LB69 G001_SLAS904.png Figure 123. FFT for 10-MHz Input Signal
ADS42LB49 ADS42LB69 G002_SLAS904.png Figure 124. FFT for 170-MHz Input Signal