ZHCS367E July   2011  – January 2016 ADS4249

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 ADS424x, ADS422x Family Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: ADS4249 (250 MSPS)
    6. 7.6  Electrical Characteristics: General
    7. 7.7  Digital Characteristics
    8. 7.8  LVDS and CMOS Modes Timing Requirements
    9. 7.9  LVDS Timings at Lower Sampling Frequencies
    10. 7.10 CMOS Timings at Lower Sampling Frequencies
    11. 7.11 Serial Interface Timing Characteristics
    12. 7.12 Reset Timing (Only when Serial Interface is Used)
    13. 7.13 Typical Characteristics
      1. 7.13.1 Typical Characteristics: ADS4249
      2. 7.13.2 Typical Characteristics: Contour
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital Functions
      2. 8.3.2 Gain for SFDR, SNR Trade-Off
      3. 8.3.3 Offset Correction
      4. 8.3.4 Power-Down
        1. 8.3.4.1 Global Power-Down
        2. 8.3.4.2 Channel Standby
        3. 8.3.4.3 Input Clock Stop
      5. 8.3.5 Output Data Format
    4. 8.4 Device Functional Modes
      1. 8.4.1 Output Interface Modes
        1. 8.4.1.1 Output Interface
        2. 8.4.1.2 DDR LVDS Outputs
        3. 8.4.1.3 LVDS Buffer
        4. 8.4.1.4 Parallel CMOS Interface
        5. 8.4.1.5 CMOS Interface Power Dissipation
        6. 8.4.1.6 Multiplexed Mode of Operation
    5. 8.5 Programming
      1. 8.5.1 Parallel Configuration Only
      2. 8.5.2 Serial Interface Configuration Only
      3. 8.5.3 Using Both Serial Interface and Parallel Controls
      4. 8.5.4 Parallel Configuration Details
      5. 8.5.5 Serial Interface Details
        1. 8.5.5.1 Register Initialization
        2. 8.5.5.2 Serial Register Readout
    6. 8.6 Register Maps
      1. 8.6.1 Serial Register Map
      2. 8.6.2 Description of Serial Registers
        1. 8.6.2.1  Register Address 00h (Default = 00h)
        2. 8.6.2.2  Register Address 01h (Default = 00h)
        3. 8.6.2.3  Register Address 01h (Default = 00h)
        4. 8.6.2.4  Register Address 25h (Default = 00h)
        5. 8.6.2.5  Register Address 29h (Default = 00h)
        6. 8.6.2.6  Register Address 2Bh (Default = 00h)
        7. 8.6.2.7  Register Address 3Dh (Default = 00h)
        8. 8.6.2.8  Register Address 3Fh (Default = 00h)
        9. 8.6.2.9  Register Address 40h (Default = 00h)
        10. 8.6.2.10 Register Address 41h (Default = 00h)
        11. 8.6.2.11 Register Address 42h (Default = 00h)
        12. 8.6.2.12 Register Address 45h (Default = 00h)
        13. 8.6.2.13 Register Address 4Ah (Default = 00h)
        14. 8.6.2.14 Register Address 58h (Default = 00h)
        15. 8.6.2.15 Register Address BFh (Default = 00h)
        16. 8.6.2.16 Register Address C1h (Default = 00h)
        17. 8.6.2.17 Register Address CFh (Default = 00h)
        18. 8.6.2.18 Register Address EFh (Default = 00h)
        19. 8.6.2.19 Register Address F1h (Default = 00h)
        20. 8.6.2.20 Register Address F2h (Default = 00h)
        21. 8.6.2.21 Register Address 2h (Default = 00h)
        22. 8.6.2.22 Register Address D5h (Default = 00h)
        23. 8.6.2.23 Register Address D7h (Default = 00h)
        24. 8.6.2.24 Register Address DBh (Default = 00h)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Theory of Operation
      2. 9.1.2 Analog Input
        1. 9.1.2.1 Drive Circuit Requirements
        2. 9.1.2.2 Driving Circuit
      3. 9.1.3 Clock Input
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Analog Input
        2. 9.2.2.2 Common Mode Voltage Output (VCM)
        3. 9.2.2.3 Clock Driver
        4. 9.2.2.4 Digital Interface
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Sharing DRVDD and AVDD Supplies
    2. 10.2 Using DC-DC Power Supplies
    3. 10.3 Power Supply Bypassing
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Grounding
      2. 11.1.2 Exposed Pad
      3. 11.1.3 Routing Analog Inputs
      4. 11.1.4 Routing Digital Inputs
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 开发支持
        1. 12.1.1.1 技术参数定义
    2. 12.2 文档支持
      1. 12.2.1 相关文档　
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Specifications

7.1 Absolute Maximum Ratings(1)

MIN MAX UNIT
Supply voltage, AVDD –0.3 2.1 V
Supply voltage, DRVDD –0.3 2.1 V
Voltage between AGND and DRGND –0.3 0.3 V
Voltage between AVDD to DRVDD (when AVDD leads DRVDD) –2.4 2.4 V
Voltage between DRVDD to AVDD (when DRVDD leads AVDD) –2.4 2.4 V
Voltage applied to input pins INP_A, INM_A, INP_B, INM_B –0.3 Minimum
(1.9, AVDD + 0.3)		 V
CLKP, CLKM(2) –0.3 AVDD + 0.3
RESET, SCLK, SDATA, SEN,
CTRL1, CTRL2, CTRL3		 –0.3 3.9
Operating free-air temperature, TA –40 85 °C
Operating junction temperature, TJ 125 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) When AVDD is turned off, switching off the input clock (or ensuring the voltage on CLKP, CLKM is less than |0.3 V|) is recommended. This configuration prevents the ESD protection diodes at the clock input pins from turning on.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Over operating free-air temperature range, unless otherwise noted.
MIN NOM MAX UNIT
SUPPLIES
Analog supply voltage, AVDD 1.7 1.8 1.9 V
Digital supply voltage, DRVDD 1.7 1.8 1.9 V
ANALOG INPUTS
Differential input voltage 2 VPP
Input common-mode VCM ± 0.05 V
Maximum analog input frequency with 2-VPP input amplitude(1) 400 MHz
Maximum analog input frequency with 1-VPP input amplitude(1) 600 MHz
CLOCK INPUT
Input clock sample rate Low-speed mode enabled(2) 1 80 MSPS
Low-speed mode disabled(2) (by default after reset) 80 250
Input clock amplitude differential
(VCLKP – VCLKM)		 Sine wave, ac-coupled 0.2 1.5 VPP
LVPECL, ac-coupled 1.6
LVDS, ac-coupled 0.7
LVCMOS, single-ended, ac-coupled 1.5
Input clock duty cycle Low-speed mode disabled 35% 50% 65%
Low-speed mode enabled 40% 50% 60%
DIGITAL OUTPUTS
Maximum external load capacitance from each output pin to DRGND, CLOAD 5 pF
Differential load resistance between the LVDS output pairs (LVDS mode), RLOAD 100 Ω
Operating free-air temperature, TA –40 +85 °C
(1) See the Theory of Operation section.
(2) See the Serial Interface Configuration section for details on programming the low-speed mode.

7.4 Thermal Information

THERMAL METRIC(1) ADS4249 UNIT
RGC (VQFN)
64 PINS
RθJA Junction-to-ambient thermal resistance 23.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 10.9 °C/W
RθJB Junction-to-board thermal resistance 4.3 °C/W
ψJT Junction-to-top characterization parameter 0.1 °C/W
ψJB Junction-to-board characterization parameter 4.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.6 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics: ADS4249 (250 MSPS)

Typical values are at +25°C, AVDD = 1.8 V, DRVDD = 1.8 V, 50% clock duty cycle, –1 dBFS differential analog input, LVDS interface, and 0-dB gain, unless otherwise noted. Minimum and maximum values are across the full temperature range:
TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, and DRVDD = 1.8 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 14 Bits
SNR Signal-to-noise ratio fIN = 20 MHz 72.8 dBFS
fIN = 70 MHz 72.5
fIN = 100 MHz 72.2
fIN = 170 MHz 67.5 71.7
fIN = 300 MHz 69.4
SINAD Signal-to-noise and
distortion ratio		 fIN = 20 MHz 72 dBFS
fIN = 70 MHz 71.6
fIN = 100 MHz 71.6
fIN = 170 MHz 66.5 70.7
fIN = 300 MHz 68.7
SFDR Spurious-free dynamic range fIN = 20 MHz 80 dBc
fIN = 70 MHz 79
fIN = 100 MHz 82
fIN = 170 MHz 71 80
fIN = 300 MHz 76
THD Total harmonic distortion fIN = 20 MHz 78 dBc
fIN = 70 MHz 77
fIN = 100 MHz 79
fIN = 170 MHz 69 76
fIN = 300 MHz 75
HD2 Second-order harmonic distortion fIN = 20 MHz 80 dBc
fIN = 70 MHz 79
fIN = 100 MHz 81
fIN = 170 MHz 71 80
fIN = 300 MHz 76
HD3 Third-order harmonic distortion fIN = 20 MHz 85 dBc
fIN = 70 MHz 87
fIN = 100 MHz 96
fIN = 170 MHz 71 80
fIN = 300 MHz 84
Worst spur
(other than second and third harmonics)		 fIN = 20 MHz 92 dBc
fIN = 70 MHz 95
fIN = 100 MHz 94
fIN = 170 MHz 77 88
fIN = 300 MHz 85
IMD Two-tone intermodulation distortion f1 = 46 MHz, f2 = 50 MHz,
each tone at –7 dBFS		 95 dBFS
f1 = 185 MHz, f2 = 190 MHz,
each tone at –7 dBFS		 82
Crosstalk 20-MHz full-scale signal on channel under observation; 170-MHz full-scale signal on other channel 95 dB
Input overload recovery Recovery to within 1%
(of full-scale) for 6 dB overload with sine-wave input		 1 Clock cycle
PSRR AC power-supply rejection ratio For 50-mVPP signal on AVDD supply, up to 10 MHz 30 dB
ENOB Effective number of bits fIN = 170 MHz 11.45 LSBs
DNL Differential nonlinearity fIN = 170 MHz –0.95 ±0.5 1.7 LSBs
INL Integrated nonlinearity fIN = 170 MHz ±2 ±4.5 LSBs

7.6 Electrical Characteristics: General

Typical values are at +25°C, AVDD = 1.8 V, DRVDD = 1.8 V, 50% clock duty cycle, and –1 dBFS differential analog input, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, and DRVDD = 1.8 V.
PARAMETER MIN TYP MAX UNIT
ANALOG INPUTS
Differential input voltage range 2 VPP
Differential input resistance (at 200 MHz) 0.75 kΩ
Differential input capacitance (at 200 MHz) 3.7 pF
Analog input bandwidth
(with 50-Ω source impedance, and 50-Ω termination)		 550 MHz
Analog input common-mode current
(per input pin of each channel)		 1.5 µA/MSPS
VCM Common-mode output voltage 0.95(2) V
VCM output current capability 4 mA
DC ACCURACY
Offset error –15 2.5 15 mV
Temperature coefficient of offset error 0.003 mV/°C
EGREF Gain error as a result of internal reference inaccuracy alone –2 2 %FS
EGCHAN Gain error of channel alone ±0.1 1 %FS
Temperature coefficient of EGCHAN 0.002 Δ%/°C
POWER SUPPLY
IAVDD Analog supply current 167 190 mA
IDRVDD Output buffer supply current, LVDS interface, 350-mV swing with 100-Ω external termination, fIN = 2.5 MHz 144 160 mA
IDRVDD Output buffer supply current, CMOS interface, no load capacitance, fIN = 2.5 MHz(1) 94 mA
Analog power 301 342 mW
Digital power, LVDS interface, 350-mV swing with 100-Ω external termination, fIN = 2.5 MHz 259 288 mW
Digital power, CMOS interface, 8-pF external load capacitance(1),
fIN = 2.5 MHz		 169 mW
Global power-down 25 mW
(1) In CMOS mode, the DRVDD current scales with the sampling frequency, the load capacitance on output pins, input frequency, and the supply voltage (see the CMOS Interface Power Dissipation section).
(2) VCM changes to 0.87 V when serial register bits HIGH PERF MODE[7:2] are set.

7.7 Digital Characteristics

At AVDD = 1.8 V and DRVDD = 1.8 V, unless otherwise noted. DC specifications refer to the condition where the digital outputs do not switch, but are permanently at a valid logic level 0 or 1.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, CTRL1, CTRL2, CTRL3)(1)
High-level input voltage All digital inputs support 1.8-V and 3.3-V CMOS logic levels 1.3 V
Low-level input voltage 0.4 V
High-level input current SDATA, SCLK(2) VHIGH = 1.8 V 10 µA
SEN(3) VHIGH = 1.8 V 0
Low-level input current SDATA, SCLK VLOW = 0 V 0 µA
SEN VLOW = 0 V 10
DIGITAL OUTPUTS, CMOS INTERFACE (DA[13:0], DB[13:0], CLKOUT, SDOUT)
High-level output voltage DRVDD – 0.1 DRVDD V
Low-level output voltage 0 0.1 V
DIGITAL OUTPUTS, LVDS INTERFACE
High-level output
differential voltage		 VODH With an external
100-Ω termination		 270 350 430 mV
Low-level output
differential voltage		 VODL With an external
100-Ω termination		 –430 –350 –270 mV
Output common-mode voltage VOCM 0.9 1.05 1.25 V
(1) SCLK, SDATA, and SEN function as digital input pins in serial configuration mode.
(2) SDATA, SCLK have internal 150-kΩ pull-down resistor.
(3) SEN has an internal 150-kΩ pull-up resistor to AVDD. Because the pull-up is weak, SEN can also be driven by 1.8 V or 3.3 V CMOS buffers.

7.8 LVDS and CMOS Modes Timing Requirements

Typical values are at +25°C, AVDD = 1.8 V, DRVDD = 1.8 V, sampling frequency = 250 MSPS, sine wave input clock, CLOAD = 5 pF, and RLOAD = 100 Ω, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, and DRVDD = 1.7 V to 1.9 V.(1)
MIN TYP MAX UNIT
GENERAL
tA Aperture delay 0.5 0.8 1.1 ns
Aperture delay matching between the two channels of the same device ±70 ps
Variation of aperture delay between two devices at the same temperature and DRVDD supply ±150 ps
tJ Aperture jitter 140 fS rms
Wakeup time Time to valid data after coming out of STANDBY mode 50 100 µs
Time to valid data after coming out of GLOBAL power-down mode 100 500
ADC latency(4) Default latency after reset 16 Clock cycles
Digital functions enabled (EN DIGITAL = 1) 24
DDR LVDS MODE(2)
tSU Data setup time: data valid(3) to zero-crossing of CLKOUTP 0.6 0.88 ns
tH Data hold time: zero-crossing of CLKOUTP to data becoming invalid(3) 0.33 0.55 ns
tPDI Clock propagation delay: input clock rising edge cross-over to output clock rising edge cross-over 5 6 7.5 ns
LVDS bit clock duty cycle of differential clock, (CLKOUTP-CLKOUTM) 48%
tRISE,
tFALL		 Data rise time, data fall time: rise time measured from –100 mV to +100 mV,
fall time measured from +100 mV to –100 mV,
1 MSPS ≤ sampling frequency ≤ 250 MSPS		 0.13 ns
tCLKRISE,
tCLKFALL		 Output clock rise time, output clock fall time: rise time measured from –100 mV to +100 mV, fall time measured from +100 mV to –100 mV, 1 MSPS ≤ sampling frequency ≤ 250 MSPS 0.13 ns
PARALLEL CMOS MODE
tPDI Clock propagation delay: input clock rising edge cross-over to output clock rising edge cross-over 4.5 6.2 8.5 ns
Output clock duty cycle of output clock (CLKOUT),
1 MSPS ≤ sampling frequency ≤ 200 MSPS		 50%
tRISE,
tFALL		 Data rise time, data fall time: rise time measured from 20% to 80% of DRVDD,
fall time measured from 80% to 20% of DRVDD,
1 MSPS ≤ sampling frequency ≤ 200 MSPS		 0.7 ns
tCLKRISE,
tCLKFALL		 Output clock rise time output clock fall time: rise time measured from 20% to 80% of DRVDD, fall time measured from 80% to 20% of DRVDD, 1 MSPS ≤ sampling frequency ≤ 200 MSPS 0.7 ns
(1) Timing parameters are ensured by design and characterization and not tested in production.
(2) Measurements are done with a transmission line of 100-Ω characteristic impedance between the device and the load. Setup and hold time specifications take into account the effect of jitter on the output data and clock.
(3) Data valid refers to a logic high of +100 mV and a logic low of –100 mV.
(4) At higher frequencies, tPDI is greater than one clock period and overall latency = ADC latency + 1.

7.9 LVDS Timings at Lower Sampling Frequencies

Typical values are at +25°C, AVDD = 1.8 V, DRVDD = 1.8 V, sampling frequency = 250 MSPS, sine wave input clock, CLOAD = 5 pF, and RLOAD = 100 Ω, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, and DRVDD = 1.7 V to 1.9 V.
SAMPLING FREQUENCY (MSPS) SETUP TIME (ns) HOLD TIME (ns) tPDI, CLOCK PROPAGATION
DELAY (ns)
MIN TYP MAX MIN TYP MAX MIN TYP MAX
65 5.9 6.6 0.35 0.6 5 6 7.5
80 4.5 5.2 0.35 0.6 5 6 7.5
125 2.3 2.9 0.35 0.6 5 6 7.5
160 1.5 2 0.33 0.55 5 6 7.5
185 1.3 1.6 0.33 0.55 5 6 7.5
200 1.1 1.4 0.33 0.55 5 6 7.5
230 0.76 1.06 0.33 0.55 5 6 7.5

7.10 CMOS Timings at Lower Sampling Frequencies

Typical values are at +25°C, AVDD = 1.8 V, DRVDD = 1.8 V, sampling frequency = 250 MSPS, sine wave input clock, CLOAD = 5 pF, and RLOAD = 100 Ω, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, and DRVDD = 1.7 V to 1.9 V.
SAMPLING FREQUENCY (MSPS) TIMINGS SPECIFIED WITH RESPECT TO CLKOUT
SETUP TIME(1) (ns) HOLD TIME(1) (ns) tPDI, CLOCK PROPAGATION
DELAY (ns)
MIN TYP MAX MIN TYP MAX MIN TYP MAX
65 6.1 6.7 6.7 7.5 4.5 6.2 8.5
80 4.7 5.2 5.3 6 4.5 6.2 8.5
125 2.7 3.1 3.1 3.6 4.5 6.2 8.5
160 1.6 2.1 2.3 2.8 4.5 6.2 8.5
185 1.1 1.6 1.9 2.4 4.5 6.2 8.5
200 1 1.4 1.7 2.2 4.5 6.2 8.5
(1) In CMOS mode, setup time is measured from the beginning of data valid to 50% of the CLKOUT rising edge, whereas hold time is measured from 50% of the CLKOUT rising edge to data becoming invalid. Data valid refers to a logic high of 1.26 V and a logic low of 0.54 V.

7.11 Serial Interface Timing Characteristics

Typical values at +25°C; minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = +85°C,
AVDD = 1.8 V, and DRVDD = 1.8 V, unless otherwise noted.
MIN TYP MAX UNIT
fSCLK SCLK frequency (equal to 1 / tSCLK) > dc 20 MHz
tSLOADS SEN to SCLK setup time 25 ns
tSLOADH SCLK to SEN hold time 25 ns
tDSU SDATA setup time 25 ns
tDH SDATA hold time 25 ns

7.12 Reset Timing (Only when Serial Interface is Used)

Typical values at +25°C; minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = +85°C, unless otherwise noted.
MIN TYP MAX UNIT
t1 Power-on delay from AVDD and DRVDD power-up to active RESET pulse 1 ms
t2 Reset pulse duration; active RESET signal pulse duration 10 ns
1 µs
t3 Register write delay from RESET disable to SEN active 100 ns
ADS4249 tim_lvds_vo_level_bas550.gif
1. With external 100-Ω termination.
Figure 1. LVDS Output Voltage Levels
ADS4249 tim_cmos_iface_bas533.gif
1. Dn = bits D0, D1, D2, and so forth, of channels A and B.
Figure 2. CMOS Interface Timing Diagram
ADS4249 tim_latency_bas534.gif
1. ADC latency after reset. At higher sampling frequencies, tPDI is greater than one clock cycle, which then makes the overall latency = ADC latency + 1.
2. E = even bits (D0, D2, D4, and so forth); O = odd bits (D1, D3, D5, and so forth).
Figure 3. Latency Timing Diagram
ADS4249 tim_lvds_iface_bas534.gif Figure 4. LVDS Interface Timing Diagram
ADS4249 tim_serial_iface_bas534.gif Figure 5. Serial Interface Timing
ADS4249 tim_reset_bas533.gif

NOTE:

A high pulse on the RESET pin is required in the serial interface mode when initialized through a hardware reset. For parallel interface operation, RESET must be permanently tied high.
Figure 6. Reset Timing Diagram

7.13 Typical Characteristics

7.13.1 Typical Characteristics: ADS4249

At TA = +25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, High-Performance Mode enabled, 0-dB gain, DDR LVDS output interface, and 32k point FFT, unless otherwise noted.
ADS4249 tc_fft_10mhz_bas534.png Figure 7. Input Signal (10 MHz)
ADS4249 tc_fft_300mhz_bas534.png Figure 9. Input Signal (300 MHz)
ADS4249 tc_fft_2tone_ver2_bas534.png Figure 11. Two-Tone Input Signal
ADS4249 tc_snr-fin_bas534.png Figure 13. SNR vs Input Frequency
ADS4249 tc_sinad-g_fin_bas534.png Figure 15. SINAD vs Gain and Input Frequency
ADS4249 tc_perf-inamp_ver2_bas534.png Figure 17. Performance vs Input Amplitude
ADS4249 tc_perf-in_vcm_ver2_bas534.png Figure 19. Performance vs Input Common-Mode Voltage
ADS4249 tc_snr-tmp_avdd_bas534.png Figure 21. SNR vs Temperature and AVDD Supply
ADS4249 tc_perf-in_clk_amp_ver1_bas534.png Figure 23. Performance vs Input Clock Amplitude
ADS4249 tc_perf-in_clk_dcy_bas534.png Figure 25. Performance vs Input Clock Duty Cycle
ADS4249 tc_cmrr_bas534.gif Figure 27. CMRR Spectrum
ADS4249 tc_psrr_bas534.gif Figure 29. Zoomed View of PSRR Spectrum
ADS4249 tc_digi_pwr_bas534.png Figure 31. Digital Power LVDS CMOS
ADS4249 tc_fft_150mhz_bas534.png Figure 8. Input Signal (150 MHz)
ADS4249 tc_fft_2tone_ver1_bas534.png Figure 10. Two-Tone Input Signal
ADS4249 tc_sfdr-fin_bas534.png Figure 12. SFDR vs Input Frequency
ADS4249 tc_sfdr-g_fin_bas534.png Figure 14. SFDR vs Gain and Input Frequency
ADS4249 tc_perf-inamp_ver1_bas534.png Figure 16. Performance vs Input Amplitude
ADS4249 tc_perf-in_vcm_ver1_bas534.png Figure 18. Performance vs Input Common-Mode Voltage
ADS4249 tc_sfdr-tmp_avdd_bas534.png Figure 20. SFDR vs Temperature and AVDD Supply
ADS4249 tc_perf-drvdd_bas534.png Figure 22. Performance vs DRVDD Supply Voltage
ADS4249 tc_perf-in_clk_amp_ver2_bas534.png Figure 24. Performance vs Input Clock Amplitude
ADS4249 tc_cmrr-test_bas534.png Figure 26. CMRR vs Test Signal Frequency
ADS4249 tc_psrr-test_bas534.png Figure 28. PSRR vs Test Signal Frequency
ADS4249 tc_ana_pwr-fsample_bas534.png Figure 30. Analog Power vs Sampling Frequency
ADS4249 tc_digi_pwr_various_bas534.png Figure 32. Digital Power in Various Modes

7.13.2 Typical Characteristics: Contour

All graphs are at +25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, High-Performance Mode disabled, 0-dB gain, DDR LVDS output interface, and 32k point FFT, unless otherwise noted.
ADS4249 tc_contour_sfdr_0db_bas534.gif Figure 33. Spurious-Free Dynamic Range (0-dB Gain)
ADS4249 tc_contour_sfdr_6db_bas534.gif Figure 34. Spurious-Free Dynamic Range (6-dB Gain)
ADS4249 tc_contour_snr_0db_bas534.gif Figure 35. Signal-to-Noise Ratio (0-dB Gain)
ADS4249 tc_contour_snr_6db_bas534.gif Figure 36. Signal-to-Noise Ratio (6-dB Gain)