ZHCSO81 November   2021 ADS130B04-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Noise Measurements
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input ESD Protection Circuitry
      2. 8.3.2 Input Multiplexer
      3. 8.3.3 Programmable Gain Amplifier (PGA)
      4. 8.3.4 Voltage Reference
      5. 8.3.5 Internal Test Signals
      6. 8.3.6 Clocking
        1. 8.3.6.1 External Clock Using CLKIN Pin
        2. 8.3.6.2 Internal Oscillator
      7. 8.3.7 ΔΣ Modulator
      8. 8.3.8 Digital Filter
        1. 8.3.8.1 Digital Filter Implementation
          1. 8.3.8.1.1 Fast-Settling Filter
          2. 8.3.8.1.2 SINC3 and SINC3 + SINC1 Filter
        2. 8.3.8.2 Digital Filter Characteristic
      9. 8.3.9 Register Map CRC
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Up and Reset
        1. 8.4.1.1 Power-On Reset
        2. 8.4.1.2 SYNC/RESET Pin
        3. 8.4.1.3 RESET Command
      2. 8.4.2 Fast Start-Up Behavior
      3. 8.4.3 Conversion Modes
        1. 8.4.3.1 Continuous-Conversion Mode
        2. 8.4.3.2 Global-Chop Mode
      4. 8.4.4 Power Modes
      5. 8.4.5 Standby Mode
      6. 8.4.6 Synchronization
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1  Chip Select (CS)
        2. 8.5.1.2  Serial Data Clock (SCLK)
        3. 8.5.1.3  Serial Data Input (DIN)
        4. 8.5.1.4  Serial Data Output (DOUT)
        5. 8.5.1.5  Data Ready (DRDY)
        6. 8.5.1.6  SPI Communication Frames
        7. 8.5.1.7  SPI Communication Words
        8. 8.5.1.8  Short SPI Frames
        9. 8.5.1.9  Communication Cyclic Redundancy Check (CRC)
        10. 8.5.1.10 SPI Timeout
      2. 8.5.2 ADC Conversion Data Format
      3. 8.5.3 Commands
        1. 8.5.3.1 NULL (0000 0000 0000 0000)
        2. 8.5.3.2 RESET (0000 0000 0001 0001)
        3. 8.5.3.3 STANDBY (0000 0000 0010 0010)
        4. 8.5.3.4 WAKEUP (0000 0000 0011 0011)
        5. 8.5.3.5 LOCK (0000 0101 0101 0101)
        6. 8.5.3.6 UNLOCK (0000 0110 0110 0110)
        7. 8.5.3.7 RREG (101a aaaa annn nnnn)
          1. 8.5.3.7.1 Reading a Single Register
          2. 8.5.3.7.2 Reading Multiple Registers
        8. 8.5.3.8 WREG (011a aaaa annn nnnn)
      4. 8.5.4 Collecting Data for the First Time or After a Pause in Data Collection
    6. 8.6 Register Map
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Troubleshooting
      2. 9.1.2 Unused Inputs and Outputs
      3. 9.1.3 Antialias Filter
      4. 9.1.4 Minimum Interface Connections
      5. 9.1.5 Multiple Device Configuration
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Current Shunt Measurement
        2. 9.2.2.2 Battery Pack Voltage Measurement
        3. 9.2.2.3 Shunt Temperature Measurement
        4. 9.2.2.4 Auxiliary Analog Supply Voltage Measurement
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 CAP Pin Capacitor Requirement
    2. 10.2 Power-Supply Sequencing
    3. 10.3 Power-Supply Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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8.6 Register Map

Table 8-10 lists the ADS130B04-Q1 registers. All register addresses not listed in Table 8-10 should be considered as reserved locations with the default setting of 0000h and the register contents should not be modified from its default setting.

Table 8-10 Register Map
ADDRESS REGISTER RESET VALUE BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
DEVICE SETTINGS AND STATUS INDICATORS (Read-Only Registers)
00h ID 54xxh RESERVED CHANCNT[3:0]
RESERVED
01h STATUS 0500h LOCK F_RESYNC REG_MAP CRC_ERR CRC_TYPE RESET WLENGTH[1:0]
RESERVED DRDY3 DRDY2 DRDY1 DRDY0
GLOBAL SETTINGS ACROSS CHANNELS
02h MODE 0510h RESERVED REGCRC_EN RX_CRC_EN CRC_TYPE RESET WLENGTH[1:0]
RESERVED TIMEOUT RESERVED DRDY_HiZ RESERVED
03h CLOCK 0F8Eh RESERVED CH3_EN CH2_EN CH1_EN CH0_EN
CLK_SEL RESERVED OSR[2:0] PWR[1:0]
04h GAIN 0000h RESERVED PGAGAIN3[2:0] RESERVED PGAGAIN2[2:0]
RESERVED PGAGAIN1[2:0] RESERVED PGAGAIN0[2:0]
06h GLOBAL_CHOP_CFG 0600h RESERVED GC_DLY[3:0] GC_EN
RESERVED
CHANNEL-SPECIFIC SETTINGS
09h CH0_CFG 0000h RESERVED
RESERVED MUX0[1:0]
0Ch RESERVED 8000h RESERVED
RESERVED
0Eh CH1_CFG 0000h RESERVED
RESERVED MUX1[1:0]
11h RESERVED 8000h RESERVED
RESERVED
13h CH2_CFG 0000h RESERVED
RESERVED MUX2[1:0]
16h RESERVED 8000h RESERVED
RESERVED
18h CH3_CFG 0000h RESERVED
RESERVED MUX3[1:0]
1Bh RESERVED 8000h RESERVED
RESERVED
REGISTER MAP CRC REGISTER (Read-Only Register)
3Eh REGMAP_CRC 0000h REG_CRC[15:8]
REG_CRC[7:0]

Table 8-11 shows the codes that are used for access types in this section.

Table 8-11 Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

8.6.1 ID Register (Address = 00h) [reset = 54xxh]

The ID register is shown in Figure 8-24 and described in Table 8-12.

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Figure 8-24 ID Register
15 14 13 12 11 10 9 8
RESERVED CHANCNT[3:0]
R-0101b R-0100b
7 6 5 4 3 2 1 0
RESERVED
R-xxxxxxxxb
Table 8-12 ID Register Field Descriptions
Bit Field Type Reset Description
15:12 RESERVED R 0101b Reserved
Always reads 0101b
11:8 CHANCNT[3:0] R 0100b Channel count
Always reads 0100b
7:0 RESERVED R xxxxxxxxb Reserved
Values are subject to change without notice

8.6.2 STATUS Register (Address = 01h) [reset = 0500h]

The STATUS register is shown in Figure 8-25 and described in Table 8-13.

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Figure 8-25 STATUS Register
15 14 13 12 11 10 9 8
LOCK F_RESYNC REG_MAP CRC_ERR CRC_TYPE RESET WLENGTH[1:0]
R-0b R-0b R-0b R-0b R-0b R-1b R-01b
7 6 5 4 3 2 1 0
RESERVED DRDY3 DRDY2 DRDY1 DRDY0
R-0000b R-0b R-0b R-0b R-0b
Table 8-13 STATUS Register Field Descriptions
Bit Field Type Reset Description
15 LOCK R 0b SPI interface lock indicator
0b = Unlocked
1b = Locked
14 F_RESYNC R 0b ADC resynchronization indicator
Bit is set each time the ADC resynchronizes.
0b = No resynchronization
1b = Resynchronization occurred
13 REG_MAP R 0b Register map CRC fault indicator
0b = No change in the register map CRC
1b = register map CRC changed
12 CRC_ERR R 0b SPI input CRC error indicator
0b = No CRC error
1b = Input CRC error occurred
11 CRC_TYPE R 0b CRC type indicator
0b = 16 bit CCITT
1b = 16 bit ANSI
10 RESET R 1b Reset status indicator
0b = No reset occurred
1b = Reset occurred
9:8 WLENGTH[1:0] R 01b Data word length indicator
00b = 16 bit
01b = 24 bits
10b = 32 bits: LSB zero padding
11b = Reserved
7:4 RESERVED R 0000b Reserved
Always reads 0000b
3 DRDY3 R 0b Channel 3 ADC data available indicator
0b = No new data available
1b = New data available
2 DRDY2 R 0b Channel 2 ADC data available indicator
0b = No new data available
1b = New data available
1 DRDY1 R 0b Channel 1 ADC data available indicator
0b = No new data available
1b = New data available
0 DRDY0 R 0b Channel 0 ADC data available indicator
0b = No new data available
1b = New data available

8.6.3 MODE Register (Address = 02h) [reset = 0510h]

The MODE register is shown in Figure 8-26 and described in Table 8-14.

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Figure 8-26 MODE Register
15141312111098
RESERVEDREG_CRC_ENRX_CRC_ENCRC_TYPERESETWLENGTH[1:0]
R/W-00bR/W-0bR/W-0bR/W-0bR/W-1bR/W-01b
76543210
RESERVEDTIMEOUTRESERVEDDRDY_HiZRESERVED
R/W-000bR/W-1bR/W-00bR/W-0bR/W-0b
Table 8-14 MODE Register Field Descriptions
BitFieldTypeResetDescription
15:14RESERVEDR/W00bReserved
Always write 00b
13REG_CRC_ENR/W0bRegister map CRC enable
0b = Disabled
1b = Enabled
12RX_CRC_ENR/W0bSPI input CRC enable
0b = Disabled
1b = Enabled
11CRC_TYPER/W0bSPI and register map CRC type selection
0b = 16 bit CCITT
1b = 16 bit ANSI
10RESETR/W1bReset
Write 0b to clear this bit in the STATUS register
0b = No reset occurred
1b = Reset occurred
9:8WLENGTH[1:0]R/W01bData word length selection
00b = 16 bits
01b = 24 bits
10b = 32 bits: LSB zero padding
11b = Reserved. Do not use.
7:5RESERVEDR/W000bReserved
Always write 000b
4TIMEOUTR/W1bSPI Timeout enable
0b = Disabled
1b = Enabled
3:2RESERVEDR/W00bReserved
Always write 00b
1DRDY_HiZR/W0bDRDY pin state selection when conversion data is not available
0b = Logic high
1b = High impedance
0RESERVEDR/W0bReserved
Always write 0b

8.6.4 CLOCK Register (Address = 03h) [reset = 0F8Eh]

The CLOCK register is shown in Figure 8-27 and described in Table 8-15.

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Figure 8-27 CLOCK Register
15 14 13 12 11 10 9 8
RESERVED CH3_EN CH2_EN CH1_EN CH0_EN
R-0000b R/W-1b R/W-1b R/W-1b R/W-1b
7 6 5 4 3 2 1 0
CLK_SEL RESERVED OSR[2:0] PWR[1:0]
R/W-1b R/W-00b R/W-011b R/W-10b
Table 8-15 CLOCK Register Field Descriptions
Bit Field Type Reset Description
15:12 RESERVED R 0000b Reserved
Always reads 0000b
11 CH3_EN R/W 1b Channel 3 ADC enable
0b = Disabled
1b = Enabled
10 CH2_EN R/W 1b Channel 2 ADC enable
0b = Disabled
1b = Enabled
9 CH1_EN R/W 1b Channel 1 ADC enable
0b = Disabled
1b = Enabled
8 CH0_EN R/W 1b Channel 0 ADC enable
0b = Disabled
1b = Enabled
7 CLK_SEL R/W 1b Clock source selection
0b = Internal oscillator
1b = External clock
6:5 RESERVED R/W 00b Reserved
Always write 00b
4:2 OSR[2:0] R/W 011b Modulator oversampling ratio selection
000b = 128
001b = 256
010b = 512
011b = 1024
100b = 2048
101b = 4096
110b = 8192
111b = 16384
1:0 PWR[1:0] R/W 10b Power mode selection
00b = Very-low power
01b = Low power
10b = High resolution
11b = High resolution

8.6.5 GAIN Register (Address = 04h) [reset = 0000h]

The GAIN register is shown in Figure 8-28 and described in Table 8-16.

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Figure 8-28 GAIN Register
15 14 13 12 11 10 9 8
RESERVED PGAGAIN3[2:0] RESERVED PGAGAIN2[2:0]
R/W-0b R/W-000b R/W-0b R/W-000b
7 6 5 4 3 2 1 0
RESERVED PGAGAIN1[2:0] RESERVED PGAGAIN0[2:0]
R/W-0b R/W-000b R/W-0b R/W-000b
Table 8-16 GAIN Register Field Descriptions
Bit Field Type Reset Description
15 RESERVED R/W 0b Reserved
Always write 0b
14:12 PGAGAIN3[2:0] R/W 000b PGA gain selection for channel 3
000b = 1
001b = 2
010b = 4
011b = 8
100b = 16
101b = 32
110b = 64
111b = 128
11 RESERVED R/W 0b Reserved
Always write 0b
10:8 PGAGAIN2[2:0] R/W 000b PGA gain selection for channel 2
000b = 1
001b = 2
010b = 4
011b = 8
100b = 16
101b = 32
110b = 64
111b = 128
7 RESERVED R/W 0b Reserved
Always write 0b
6:4 PGAGAIN1[2:0] R/W 000b PGA gain selection for channel 1
000b = 1
001b = 2
010b = 4
011b = 8
100b = 16
101b = 32
110b = 64
111b = 128
3 RESERVED R/W 0b Reserved
Always write 0b
2:0 PGAGAIN0[2:0] R/W 000b PGA gain selection for channel 0
000b = 1
001b = 2
010b = 4
011b = 8
100b = 16
101b = 32
110b = 64
111b = 128

8.6.6 GLOBAL_CHOP_CFG Register (Address = 06h) [reset = 0600h]

The GLOBAL_CHOP_CFG register is shown in Figure 8-29 and described in Table 8-17.

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Figure 8-29 GLOBAL_CHOP_CFG Register
15141312111098
RESERVEDGC_DLY[3:0]GC_EN
R/W-000bR/W-0011bR/W-0b
76543210
RESERVED
R/W-00000000b
Table 8-17 GLOBAL_CHOP_CFG Register Field Descriptions
BitFieldTypeResetDescription
15:13RESERVEDR/W000bReserved
Always write 000b
12:9GC_DLY[3:0]R/W0011bGlobal chop delay selection
Delay in modulator clock periods (tMOD) before measurement begins.
0000b = 2
0001b = 4
0010b = 8
0011b = 16
0100b = 32
0101b = 64
0110b = 128
0111b = 256
1000b = 512
1001b = 1024
1010b = 2048
1011b = 4096
1100b = 8192
1101b = 16484
1110b = 32768
1111b = 65536
8GC_ENR/W0bGlobal chop enable
0b = Disabled
1b = Enabled
7:0RESERVEDR/W00000000bReserved
Always write 00000000b

8.6.7 CH0_CFG Register (Address = 09h) [reset = 0000h]

The CH0_CFG register is shown in Figure 8-30 and described in Table 8-18.

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Figure 8-30 CH0_CFG Register
15141312111098
RESERVED
R/W-00000000b
76543210
RESERVEDRESERVEDRESERVEDMUX0[1:0]
R/W-00bR-000bR/W-0bR/W-00b
Table 8-18 CH0_CFG Register Field Descriptions
BitFieldTypeResetDescription
15:6RESERVEDR/W00000000
00b		Reserved
Always write 0000000000b
5:3RESERVEDR000bReserved
Always reads 000b
2RESERVEDR/W0bReserved
Always write 0b
1:0MUX0[1:0]R/W00bChannel 0 input selection
00b = AIN0P and AIN0N
01b = AIN0 disconnected, ADC inputs shorted
10b = Positive dc test signal
11b = Negative dc test signal

8.6.8 CH1_CFG Register (Address = 0Eh) [reset = 0000h]

The CH1_CFG register is shown in Figure 8-31 and described in Table 8-19.

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Figure 8-31 CH1_CFG Register
15 14 13 12 11 10 9 8
RESERVED
R/W-00000000b
7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED MUX1[1:0]
R/W-00b R-000b R/W-0b R/W-00b
Table 8-19 CH1_CFG Register Field Descriptions
Bit Field Type Reset Description
15:6 RESERVED R/W 00000000
00b		 Reserved
Always write 0000000000b
5:3 RESERVED R 000b Reserved
Always reads 000b
2 RESERVED R/W 0b Reserved
Always write 0b
1:0 MUX1[1:0] R/W 00b Channel 1 input selection
00b = AIN1P and AIN1N
01b = AIN1 disconnected, ADC inputs shorted
10b = Positive dc test signal
11b = Negative dc test signal

8.6.9 CH2_CFG Register (Address = 13h) [reset = 0000h]

The CH2_CFG register is shown in Figure 8-32 and described in Table 8-20.

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Figure 8-32 CH2_CFG Register
15 14 13 12 11 10 9 8
RESERVED
R/W-00000000b
7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED MUX2[1:0]
R/W-00b R-000b R/W-0b R/W-00b
Table 8-20 CH2_CFG Register Field Descriptions
Bit Field Type Reset Description
15:6 RESERVED R/W 00000000
00b		 Reserved
Always write 0000000000b
5:3 RESERVED R 000b Reserved
Always reads 000b
2 RESERVED R/W 0b Reserved
Always write 0b
1:0 MUX2[1:0] R/W 00b Channel 2 input selection
00b = AIN2P and AIN2N
01b = AIN2 disconnected, ADC inputs shorted
10b = Positive dc test signal
11b = Negative dc test signal

8.6.10 CH3_CFG Register (Address = 18h) [reset = 0000h]

The CH3_CFG register is shown in Figure 8-33 and described in Table 8-21.

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Figure 8-33 CH3_CFG Register
15 14 13 12 11 10 9 8
RESERVED
R/W-00000000b
7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED MUX3[1:0]
R/W-00b R-000b R/W-0b R/W-00b
Table 8-21 CH3_CFG Register Field Descriptions
Bit Field Type Reset Description
15:6 RESERVED R/W 00000000
00b		 Reserved
Always write 0000000000b
5:3 RESERVED R 000b Reserved
Always reads 000b
2 RESERVED R/W 0b Reserved
Always write 0b
1:0 MUX3[1:0] R/W 00b Channel 3 input selection
00b = AIN3P and AIN3N
01b = AIN3 disconnected, ADC inputs shorted
10b = Positive dc test signal
11b = Negative dc test signal

8.6.11 REGMAP_CRC Register (Address = 3Eh) [reset = 0000h]

The REGMAP_CRC register is shown in Figure 8-34 and described in Table 8-22.

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Figure 8-34 REGMAP_CRC Register
15141312111098
REG_CRC[15:8]
R-00000000b
76543210
REG_CRC[7:0]
R-00000000b
Table 8-22 REGMAP_CRC Register Field Descriptions
BitFieldTypeResetDescription
15:0REG_CRC[15:0]R00000000
00000000b		Register map CRC value