ZHCSQN6 May   2022 ADC3644

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - Power Consumption
    6. 6.6 Electrical Characteristics - DC Specifications
    7. 6.7 Electrical Characteristics - AC Specifications
    8. 6.8 Timing Requirements
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Analog Input Bandwidth
        2. 8.3.1.2 Analog Front End Design
          1. 8.3.1.2.1 Sampling Glitch Filter Design
          2. 8.3.1.2.2 Single Ended Input
          3. 8.3.1.2.3 Analog Input Termination and DC Bias
            1. 8.3.1.2.3.1 AC-Coupling
            2. 8.3.1.2.3.2 DC-Coupling
      2. 8.3.2 Clock Input
        1. 8.3.2.1 Clock Amplitude
        2. 8.3.2.2 Single Ended vs Differential Clock Input
      3. 8.3.3 Voltage Reference
        1. 8.3.3.1 Internal voltage reference
        2. 8.3.3.2 External voltage reference (VREF)
        3. 8.3.3.3 External voltage reference with internal buffer (REFBUF)
      4. 8.3.4 Digital Down Converter
        1. 8.3.4.1 DDC MUX
        2. 8.3.4.2 Digital Filter Operation
        3. 8.3.4.3 FS/4 Mixing with Real Output
        4. 8.3.4.4 Numerically Controlled Oscillator (NCO) and Digital Mixer
        5. 8.3.4.5 Decimation Filter
        6. 8.3.4.6 SYNC
        7. 8.3.4.7 Output Formatting with Decimation
          1. 8.3.4.7.1 Parallel CMOS
          2. 8.3.4.7.2 Serialized CMOS Interface
      5. 8.3.5 Digital Interface
        1. 8.3.5.1 Parallel CMOS Output
        2. 8.3.5.2 Serialized CMOS output
          1. 8.3.5.2.1 SDR Output Clocking
        3. 8.3.5.3 Output Data Format
        4. 8.3.5.4 Output Formatter
        5. 8.3.5.5 Output Bit Mapper
        6. 8.3.5.6 Output Interface or Mode Configuration
          1. 8.3.5.6.1 Configuration Example
      6. 8.3.6 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal operation
      2. 8.4.2 Power Down Options
    5. 8.5 Programming
      1. 8.5.1 Configuration using PINs only
      2. 8.5.2 Configuration using the SPI interface
        1. 8.5.2.1 Register Write
        2. 8.5.2.2 Register Read
    6. 8.6 Register Maps
      1. 8.6.1 Detailed Register Description
  9. 9 Application Information Disclaimer
    1. 9.1 Typical Application
      1. 9.1.1 Design Requirements
      2. 9.1.2 Detailed Design Procedure
        1. 9.1.2.1 Input Signal Path
        2. 9.1.2.2 Sampling Clock
        3. 9.1.2.3 Voltage Reference
      3. 9.1.3 Application Curves
    2. 9.2 Initialization Set Up
      1. 9.2.1 Register Initialization During Operation
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support (Optional)
      1. 10.1.1 Development Support (Optional)
      2. 10.1.2 Device Nomenclature (Optional)
    2. 10.2 Documentation Support (if applicable)
      1. 10.2.1 Related Documentation
    3. 10.3 接收文档更新通知
    4. 10.4 支持资源
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 术语表
  11. 11Mechanical, Packaging, and Orderable Information

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6.6 Electrical Characteristics - DC Specifications

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 105°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD, IOVDD = 1.8 V, external 1.6 V reference, 5 pF output load, and –1-dBFS differential input, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC ACCURACY
No missing codes 14 bits
PSRR FIN = 1 MHz 35 dB
DC ACCURACY
DNL Differential nonlinearity FIN = 5 MHz ± 0.5 ± 0.97 LSB
INL Integral nonlinearity FIN = 5 MHz ± 1.5 ± 7.5 LSB
VOS_ERR Offset error 8 65 LSB
VOS_DRIFT Offset drift over temperature 0.02 LSB/ºC
GAINERR Gain error External 1.6 V reference 0.5 %FSR
GAINDRIFT Gain drift over temperature External 1.6 V reference 9 ppm/ºC
GAINERR Gain error Internal reference -0.4 %FSR
GAINDRIFT Gain drift over temperature Internal reference 74 ppm/ºC
Transition Noise 0.71 LSBRMS
ADC ANALOG INPUT (AINP/M, BINP/M)
FS Input full scale Default, differential  2.25 Vpp
VCM Input common mode voltage 0.9 0.95 1.0 V
RIN Input resistance Differential at DC 8 kΩ
CIN Input capacitance Each pin to GND 5.4 pF
VOCM Output common mode voltage 0.95 V
BW Analog input bandwidth (-3dB) 1.4 GHz
Internal Voltage Reference
VREF Internal reference voltage 1.6 V
VREF Output Impedance 8 Ω
Reference Input Buffer (REFBUF)
External reference voltage 1.2 V
External voltage reference (VREF)
VREF External voltage reference 1.6 V
Input Current 1 mA
Input impedance 5.3 kΩ
Clock Input (CLKP/M)
Input clock frequency 0.01 125 125 MHz
VID Differential input voltage 250 1000 2000 mV
VCM Input common mode voltage 0.9 V
Clock duty cycle 40 50 60 %
Digital Inputs (RESET, PDN, SCLK, SEN, SDIO)
VIH High level input voltage 1.4 V
VIL Low level input voltage 0.4
IIH High level input current 90 150 uA
IIL Low level input current -150 -90
CI Input capacitance 1.5 pF
Digital Output (SDOUT)
VOH High level output voltage ILOAD = -400 uA IOVDD – 0.1 IOVDD V
VOL Low level output voltage ILOAD = 400 uA 0.1
CMOS Interface (DA0:DA6, DB0:DB6, DCLK)
Output data rate per CMOS output pin 250 MHz
VOH High level output voltage ILOAD = -400 uA IOVDD – 0.1 IOVDD V
VOL Low level output voltage ILOAD = 400 uA 0.1
VIH High level input voltage Input clock (Serial CMOS) IOVDD – 0.1 IOVDD V
VIL Low level input voltage 0.1