SLFS078B October 2006 – October 2015 TLC555-Q1
The TLC555-Q1 is a monolithic timing circuit fabricated using the TI LinCMOS™ process. The timer is fully compatible with CMOS, TTL, and MOS logic and operates at frequencies up to 2 MHz. Because of its high input impedance, this device uses smaller timing capacitors than those used by the NE555. As a result, more accurate time delays and oscillations are possible. Power consumption is low across the full range of power-supply voltage.
Like the NE555, the TLC555-Q1 has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal (CONT).
When the trigger input (TRIG) falling below the trigger level sets the flip-flop, and the output goes high. Having TRIG above the trigger level and the threshold input (THRES) above the threshold level resets the flip-flop, and the output is low. The reset input (RESET) can override all other inputs, and a possible use is to initiate a new timing cycle. RESET going low resets the flip-flop, and the output is low. Whenever the output is low, a low-impedance path exists between the discharge terminal (DISCH) and GND. Tie all unused inputs to an appropriate logic level to prevent false triggering.
|PART NUMBER||PACKAGE||BODY SIZE (NOM)|
|TLC555-Q1||SOIC (8)||4.90 mm × 3.91 mm|