SLASEC3A August   2016  – August 2016 MSP430F6459-HIREL

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    7. 5.7  Schmitt-Trigger Inputs - General-Purpose I/O
    8. 5.8  Leakage Current - General-Purpose I/O
    9. 5.9  Outputs - General-Purpose I/O (Full Drive Strength)
    10. 5.10 Outputs - General-Purpose I/O (Reduced Drive Strength)
    11. 5.11 Thermal Resistance Characteristics for PZ Package
    12. 5.12 Typical Characteristics - Outputs, Reduced Drive Strength (PxDS.y = 0)
    13. 5.13 Typical Characteristics - Outputs, Full Drive Strength (PxDS.y = 1)
    14. 5.14 Timing and Switching Characteristics
      1. 5.14.1 Power Supply Sequencing
      2. 5.14.2 Clock Specifications
      3. 5.14.3 Peripherals
      4. 5.14.4 Emulation and Debug
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Instruction Set
    4. 6.4  Operating Modes
    5. 6.5  Interrupt Vector Addresses
    6. 6.6  Memory Organization
    7. 6.7  Bootloader (BSL)
      1. 6.7.1 UART BSL
    8. 6.8  JTAG Operation
      1. 6.8.1 JTAG Standard Interface
      2. 6.8.2 Spy-Bi-Wire Interface
    9. 6.9  Flash Memory
    10. 6.10 Memory Integrity Detection (MID)
    11. 6.11 RAM
    12. 6.12 Backup RAM
    13. 6.13 Peripherals
      1. 6.13.1  Digital I/O
      2. 6.13.2  Port Mapping Controller
      3. 6.13.3  Oscillator and System Clock
      4. 6.13.4  Power-Management Module (PMM)
      5. 6.13.5  Hardware Multiplier (MPY)
      6. 6.13.6  Real-Time Clock (RTC_B)
      7. 6.13.7  Watchdog Timer (WDT_A)
      8. 6.13.8  System Module (SYS)
      9. 6.13.9  DMA Controller
      10. 6.13.10 Universal Serial Communication Interface (USCI)
      11. 6.13.11 Timer TA0
      12. 6.13.12 Timer TA1
      13. 6.13.13 Timer TA2
      14. 6.13.14 Timer TB0
      15. 6.13.15 Comparator_B
      16. 6.13.16 ADC12_A
      17. 6.13.17 DAC12_A
      18. 6.13.18 CRC16
      19. 6.13.19 Voltage Reference (REF) Module
      20. 6.13.20 LCD_B
      21. 6.13.21 LDO and PU Port
      22. 6.13.22 Embedded Emulation Module (EEM) (L Version)
      23. 6.13.23 Peripheral File Map
    14. 6.14 Input/Output Schematics
      1. 6.14.1  Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger
      2. 6.14.2  Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger
      3. 6.14.3  Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger
      4. 6.14.4  Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger
      5. 6.14.5  Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger
      6. 6.14.6  Port P5, P5.2 to P5.7, Input/Output With Schmitt Trigger
      7. 6.14.7  Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger
      8. 6.14.8  Port P7, P7.2, Input/Output With Schmitt Trigger
      9. 6.14.9  Port P7, P7.3, Input/Output With Schmitt Trigger
      10. 6.14.10 Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger
      11. 6.14.11 Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger
      12. 6.14.12 Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger
      13. 6.14.13 Port PU.0, PU.1 Ports
      14. 6.14.14 Port J, PJ.0 JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      15. 6.14.15 Port J, PJ.1 to PJ.3 JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    15. 6.15 Device Descriptors
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 General Layout Recommendations
      6. 7.1.6 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC12_B Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Detailed Design Procedure
        4. 7.2.1.4 Layout Guidelines
  8. 8Device and Documentation Support
    1. 8.1  Getting Started and Next Steps
    2. 8.2  Device Nomenclature
    3. 8.3  Tools and Software
      1. 8.3.1 Hardware Features
      2. 8.3.2 Recommended Hardware Options
        1. 8.3.2.1 Target Socket Boards
        2. 8.3.2.2 Experimenter Boards
        3. 8.3.2.3 Debugging and Programming Tools
        4. 8.3.2.4 Production Programmers
      3. 8.3.3 Recommended Software Options
        1. 8.3.3.1 Integrated Development Environments
        2. 8.3.3.2 MSP430Ware
        3. 8.3.3.3 TI-RTOS
        4. 8.3.3.4 Command-Line Programmer
    4. 8.4  Documentation Support
    5. 8.5  Receiving Notification of Documentation Updates
    6. 8.6  Community Resources
    7. 8.7  Trademarks
    8. 8.8  Electrostatic Discharge Caution
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Device Overview

1.1 Features

  • Low-Supply Voltage Range:
    3.6 V Down to 1.8 V
  • Ultra-Low-Power Consumption
    • Active Mode (AM):
      All System Clocks Active:
      295 µA/MHz at 8 MHz, 3 V, Flash Program Execution (Typical)
    • Standby Mode (LPM3):
      Watchdog With Crystal, and Supply Supervisor Operational, Full RAM Retention, Fast Wakeup:
      2 µA at 2.2 V, 2.2 µA at 3 V (Typical)
    • Shutdown, Real-Time Clock (RTC) Mode (LPM3.5):
      Shutdown Mode, Active RTC With Crystal:
      1.1 µA at 3 V (Typical)
    • Shutdown Mode (LPM4.5):
      0.45 µA at 3 V (Typical)
  • Wake up From Standby Mode in 3 µs (Typical)
  • 16-Bit RISC Architecture, Extended Memory, up to 20-MHz System Clock
  • Flexible Power-Management System
    • Fully Integrated LDO With Programmable Regulated Core Supply Voltage
    • Supply Voltage Supervision, Monitoring, and Brownout
  • Unified Clock System
    • FLL Control Loop for Frequency Stabilization
    • Low-Power Low-Frequency Internal Clock Source (VLO)
    • Low-Frequency Trimmed Internal Reference Source (REFO)
    • 32-kHz Crystals (XT1)
    • High-Frequency Crystals up to 32 MHz (XT2)
  • Four 16-Bit Timers With 3, 5, or 7 Capture/Compare Registers
  • Three Universal Serial Communication Interfaces (USCIs)
    • USCI_A0, USCI_A1, and USCI_A2 Each Support:
      • Enhanced UART With Automatic Baud-Rate Detection
      • IrDA Encoder and Decoder
      • Synchronous SPI
    • USCI_B0, USCI_B1, and USCI_B2 Each Support:
      • I2C
      • Synchronous SPI
  • 12-Bit Analog-to-Digital Converter (ADC) With Internal Shared Reference, Sample-and-Hold, and Autoscan Feature
  • Two 12-Bit Digital-to-Analog Converters (DACs) With Synchronization
  • Voltage Comparator
  • Integrated LCD Driver With Contrast Control for up to 160 Segments
  • Hardware Multiplier Supports 32-Bit Operations
  • Serial Onboard Programming, No External Programming Voltage Needed
  • Six-Channel Internal DMA
  • RTC Module With Supply Voltage Backup Switch

1.2 Applications

  • Analog and Digital Sensor Systems
  • Digital Motor Controls
  • Remote Controls
  • Thermostats
  • Digital Timers
  • Hand-Held Meters

1.3 Description

The TI MSP430™ family of ultra-low-power microcontrollers consists of several devices that feature different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows the device to wake up from low-power modes to active mode in 3 µs (typical).

The MSP430F6459-HIREL is a microcontroller configured with an integrated 3.3-V LDO, four 16-bit timers, a high-performance 12-bit ADC, three USCIs, a hardware multiplier, DMA, an RTC module with alarm capabilities, a comparator, and up to 74 I/O pins.

Typical applications for these devices include analog and digital sensor systems, digital motor control, remote controls, thermostats, digital timers, and hand-held meters.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)(2)
MSP430F6459-HIREL PZ (100) 16.0 mm × 16.0 mm
(1) For the most current device, package, and ordering information, see the Package Option Addendum in Section 9, or see the TI website at www.ti.com.
(2) The sizes shown here are approximations. For the package dimensions with tolerances, see the Mechanical Data in Section 9.

1.4 Functional Block Diagram

Figure 1-1 shows the functional block diagram for this device.

MSP430F6459-HIREL slas700-fbd-f645x-MID.gif Figure 1-1 Functional Block Diagram