SWRS223A February   2020  – August 2020 AWR2243

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Functional Block Diagram
  5. Revision History
  6. Device Comparison
    1. 6.1 Related Products
  7. Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Signal Descriptions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Power-On Hours (POH)
    4. 8.4 Recommended Operating Conditions
    5. 8.5 Power Supply Specifications
    6. 8.6 Power Consumption Summary
    7. 8.7 RF Specification
    8. 8.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    9. 8.9 Timing and Switching Characteristics
      1. 8.9.1 Power Supply Sequencing and Reset Timing
      2. 8.9.2 Synchronized Frame Triggering
      3. 8.9.3 Input Clocks and Oscillators
        1. 8.9.3.1 Clock Specifications
      4. 8.9.4 Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 8.9.4.1 Peripheral Description
          1. 8.9.4.1.1 SPI Timing Conditions
          2. 8.9.4.1.2 SPI Slave Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
          3. 8.9.4.1.3 SPI Slave Mode Timing Requirements (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        2. 8.9.4.2 Typical Interface Protocol Diagram (Slave Mode)
      5. 8.9.5 Inter-Integrated Circuit Interface (I2C)
        1. 8.9.5.1 I2C Timing Requirements
      6. 8.9.6 LVDS Interface Configuration
        1. 8.9.6.1 LVDS Interface Timings
      7. 8.9.7 General-Purpose Input/Output
        1. 8.9.7.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      8. 8.9.8 Camera Serial Interface (CSI)
        1. 8.9.8.1 CSI Switching Characteristics
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Subsystems
      1. 9.3.1 RF and Analog Subsystem
        1. 9.3.1.1 Clock Subsystem
        2. 9.3.1.2 Transmit Subsystem
        3. 9.3.1.3 Receive Subsystem
      2. 9.3.2 Host Interface
    4. 9.4 Other Subsystems
      1. 9.4.1 A2D Data Format Over CSI2 Interface
  10. 10Monitoring and Diagnostic Mechanisms
  11. 11Applications, Implementation, and Layout
    1. 11.1 Application Information
    2. 11.2 Short-, Medium-, and Long-Range Radar
    3. 11.3 Imaging Radar using Cascade Configuration
    4. 11.4 Reference Schematic
    5. 11.5 Layout
      1. 11.5.1 Layout Guidelines
      2. 11.5.2 Stackup Details
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Tools and Software
    3. 12.3 Documentation Support
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Export Control Notice
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ABL|161
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Features

  • FMCW transceiver
    • Integrated PLL, transmitter, receiver, baseband, and A2D
    • 76- to 81-GHz coverage with 5 GHz available bandwidth
    • Four receive channels
    • Three transmit channels
    • Ultra-accurate chirp engine based on Fractional-N PLL
    • TX power: 13 dBm
    • RX noise figure: 12 dB
    • Phase noise at 1 MHz:
      • –96 dBc/Hz (76 to 77 GHz)
      • –94 dBc/Hz (77 to 81 GHz)
  • Built-in calibration and self-test
    • Built-in firmware (ROM)
    • Self-calibrating system across frequency and temperature
  • Host interface
    • Control interface with external processor over SPI or I2C interface
    • Data interface with external processor over MIPI D-PHY and CSI2 v1.1
    • Interrupts for Fault Reporting
  • Functional Safety-Compliant targeted
    • Developed for functional safety applications
    • Documentation is available to aid ISO 26262 functional safety system design
    • Hardware integrity up to ASIL B targeted
    • Safety-related certification
      • ISO 26262 certification by TUV Sud planned
  • AEC-Q100 qualified
  • AWR2243 advanced features
    • Embedded self-monitoring with limited Host processor involvement
    • Complex baseband architecture
    • Option of cascading multiple devices to increase channel count
    • Embedded interference detection capability
  • Power management
    • Built-in LDO Network for enhanced PSRR
    • I/Os support dual voltage 3.3 V/1.8 V
  • Clock source
    • Supports externally driven clock (square/sine) at 40 MHz
    • Supports 40 MHz crystal connection with load capacitors
  • Easy hardware design
    • 0.65-mm pitch, 161-pin 10.4 mm × 10.4 mm flip chip BGA package for easy assembly and low-cost PCB design
    • Small solution size
  • Supports automotive temperature operating range