SBAS928A
February 2020 – June 2020
ADS7066
PRODUCTION DATA.
1
Features
2
Applications
3
Description
ADS7066 Block Diagram
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Switching Characteristics
6.8
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Analog Input and Multiplexer
7.3.2
Reference
7.3.2.1
Internal Reference
7.3.2.2
External Reference
7.3.3
ADC Transfer Function
7.3.4
ADC Offset Calibration
7.3.5
Programmable Averaging Filters
7.3.6
CRC on Data Interface
7.3.7
Oscillator and Timing Control
7.3.8
Diagnostic Modes
7.3.8.1
Bit-Walk Test Mode
7.3.8.2
Fixed Voltage Test Mode
7.3.9
Output Data Format
7.3.9.1
Status Flags
7.3.9.2
Output CRC (Device to Host)
7.3.9.3
Input CRC (Host to Device)
7.3.10
Device Programming
7.3.10.1
Enhanced-SPI Interface
7.3.10.2
Daisy-Chain Mode
7.3.10.3
Register Read/Write Operation
7.3.10.3.1
Register Write
7.3.10.3.2
Register Read
7.3.10.3.2.1
Register Read With CRC
7.4
Device Functional Modes
7.4.1
Device Power-Up and Reset
7.4.2
Manual Mode
7.4.3
On-the-Fly Mode
7.4.4
Auto-Sequence Mode
7.5
Page1 Registers
7.5.1
SYSTEM_STATUS Register (Address = 0x0) [reset = 0x81]
Table 11.
SYSTEM_STATUS Register Field Descriptions
7.5.2
GENERAL_CFG Register (Address = 0x1) [reset = 0x0]
Table 12.
GENERAL_CFG Register Field Descriptions
7.5.3
DATA_CFG Register (Address = 0x2) [reset = 0x0]
Table 13.
DATA_CFG Register Field Descriptions
7.5.4
OSR_CFG Register (Address = 0x3) [reset = 0x0]
Table 14.
OSR_CFG Register Field Descriptions
7.5.5
OPMODE_CFG Register (Address = 0x4) [reset = 0x4]
Table 15.
OPMODE_CFG Register Field Descriptions
7.5.6
PIN_CFG Register (Address = 0x5) [reset = 0x0]
Table 16.
PIN_CFG Register Field Descriptions
7.5.7
GPIO_CFG Register (Address = 0x7) [reset = 0x0]
Table 17.
GPIO_CFG Register Field Descriptions
7.5.8
GPO_DRIVE_CFG Register (Address = 0x9) [reset = 0x0]
Table 18.
GPO_DRIVE_CFG Register Field Descriptions
7.5.9
GPO_OUTPUT_VALUE Register (Address = 0xB) [reset = 0x0]
Table 19.
GPO_OUTPUT_VALUE Register Field Descriptions
7.5.10
GPI_VALUE Register (Address = 0xD) [reset = 0x0]
Table 20.
GPI_VALUE Register Field Descriptions
7.5.11
SEQUENCE_CFG Register (Address = 0x10) [reset = 0x0]
Table 21.
SEQUENCE_CFG Register Field Descriptions
7.5.12
CHANNEL_SEL Register (Address = 0x11) [reset = 0x0]
Table 22.
CHANNEL_SEL Register Field Descriptions
7.5.13
AUTO_SEQ_CH_SEL Register (Address = 0x12) [reset = 0x0]
Table 23.
AUTO_SEQ_CH_SEL Register Field Descriptions
7.5.14
DIAGNOSTICS_KEY Register (Address = 0xBF) [reset = 0x0]
Table 24.
DIAGNOSTICS_KEY Register Field Descriptions
7.5.15
DIAGNOSTICS_EN Register (Address = 0xC0) [reset = 0x0]
Table 25.
DIAGNOSTICS_EN Register Field Descriptions
7.5.16
BIT_SAMPLE_LSB Register (Address = 0xC1) [reset = 0x0]
Table 26.
BIT_SAMPLE_LSB Register Field Descriptions
7.5.17
BIT_SAMPLE_MSB Register (Address = 0xC2) [reset = 0x0]
Table 27.
BIT_SAMPLE_MSB Register Field Descriptions
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Charge-Kickback Filter and ADC Amplifier
8.2.3
Application Curve
9
Power Supply Recommendations
9.1
AVDD and DVDD Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Device Support
11.1.1
Development Support
11.2
Documentation Support
11.2.1
Related Documentation
11.3
Receiving Notification of Documentation Updates
11.4
Support Resources
11.5
Trademarks
11.6
Electrostatic Discharge Caution
11.7
Glossary
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
YBH|16
MPBGAQ3
Thermal pad, mechanical data (Package|Pins)
Orderable Information
sbas928a_oa
sbas928a_pm
1
Features
Small solution size:
1.62-mm × 1.62-mm WCSP
Space-saving, capless, 2.5-V internal reference
8 channels configurable as any combination of:
Up to 8 analog inputs, digital inputs, or digital outputs
Programmable averaging filters:
Programmable sample size for averaging
Averaging with internal conversions
20-bit resolution for average output
Low-leakage multiplexer with channel sequencer:
Manual mode
On-the-fly mode
Auto-sequence mode
Excellent AC and DC performance:
SNR: 86 dB, THD: –100 dB
Improved SNR with programmable averaging filters
INL: ±1 LSB, 16-bit no missing codes
Internal calibration improves offset and drift
High sample rate with no latency output:
250 kSPS
Wide operating range:
ADC input range: 0 V to V
REF
and 2 x V
REF
Analog supply: 3 V to 5.5 V
Digital supply: 1.65 V to 5.5 V
Temperature range: –40°C to +125°C
Enhanced-SPI digital interface:
High-speed, 60-MHz SPI interface
Achieve full throughput with > 4.5-MHz SPI