SBAS928A February   2020  – June 2020 ADS7066

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     ADS7066 Block Diagram
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Input and Multiplexer
      2. 7.3.2  Reference
        1. 7.3.2.1 Internal Reference
        2. 7.3.2.2 External Reference
      3. 7.3.3  ADC Transfer Function
      4. 7.3.4  ADC Offset Calibration
      5. 7.3.5  Programmable Averaging Filters
      6. 7.3.6  CRC on Data Interface
      7. 7.3.7  Oscillator and Timing Control
      8. 7.3.8  Diagnostic Modes
        1. 7.3.8.1 Bit-Walk Test Mode
        2. 7.3.8.2 Fixed Voltage Test Mode
      9. 7.3.9  Output Data Format
        1. 7.3.9.1 Status Flags
        2. 7.3.9.2 Output CRC (Device to Host)
        3. 7.3.9.3 Input CRC (Host to Device)
      10. 7.3.10 Device Programming
        1. 7.3.10.1 Enhanced-SPI Interface
        2. 7.3.10.2 Daisy-Chain Mode
        3. 7.3.10.3 Register Read/Write Operation
          1. 7.3.10.3.1 Register Write
          2. 7.3.10.3.2 Register Read
            1. 7.3.10.3.2.1 Register Read With CRC
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Power-Up and Reset
      2. 7.4.2 Manual Mode
      3. 7.4.3 On-the-Fly Mode
      4. 7.4.4 Auto-Sequence Mode
    5. 7.5 Page1 Registers
      1. 7.5.1  SYSTEM_STATUS Register (Address = 0x0) [reset = 0x81]
        1. Table 11. SYSTEM_STATUS Register Field Descriptions
      2. 7.5.2  GENERAL_CFG Register (Address = 0x1) [reset = 0x0]
        1. Table 12. GENERAL_CFG Register Field Descriptions
      3. 7.5.3  DATA_CFG Register (Address = 0x2) [reset = 0x0]
        1. Table 13. DATA_CFG Register Field Descriptions
      4. 7.5.4  OSR_CFG Register (Address = 0x3) [reset = 0x0]
        1. Table 14. OSR_CFG Register Field Descriptions
      5. 7.5.5  OPMODE_CFG Register (Address = 0x4) [reset = 0x4]
        1. Table 15. OPMODE_CFG Register Field Descriptions
      6. 7.5.6  PIN_CFG Register (Address = 0x5) [reset = 0x0]
        1. Table 16. PIN_CFG Register Field Descriptions
      7. 7.5.7  GPIO_CFG Register (Address = 0x7) [reset = 0x0]
        1. Table 17. GPIO_CFG Register Field Descriptions
      8. 7.5.8  GPO_DRIVE_CFG Register (Address = 0x9) [reset = 0x0]
        1. Table 18. GPO_DRIVE_CFG Register Field Descriptions
      9. 7.5.9  GPO_OUTPUT_VALUE Register (Address = 0xB) [reset = 0x0]
        1. Table 19. GPO_OUTPUT_VALUE Register Field Descriptions
      10. 7.5.10 GPI_VALUE Register (Address = 0xD) [reset = 0x0]
        1. Table 20. GPI_VALUE Register Field Descriptions
      11. 7.5.11 SEQUENCE_CFG Register (Address = 0x10) [reset = 0x0]
        1. Table 21. SEQUENCE_CFG Register Field Descriptions
      12. 7.5.12 CHANNEL_SEL Register (Address = 0x11) [reset = 0x0]
        1. Table 22. CHANNEL_SEL Register Field Descriptions
      13. 7.5.13 AUTO_SEQ_CH_SEL Register (Address = 0x12) [reset = 0x0]
        1. Table 23. AUTO_SEQ_CH_SEL Register Field Descriptions
      14. 7.5.14 DIAGNOSTICS_KEY Register (Address = 0xBF) [reset = 0x0]
        1. Table 24. DIAGNOSTICS_KEY Register Field Descriptions
      15. 7.5.15 DIAGNOSTICS_EN Register (Address = 0xC0) [reset = 0x0]
        1. Table 25. DIAGNOSTICS_EN Register Field Descriptions
      16. 7.5.16 BIT_SAMPLE_LSB Register (Address = 0xC1) [reset = 0x0]
        1. Table 26. BIT_SAMPLE_LSB Register Field Descriptions
      17. 7.5.17 BIT_SAMPLE_MSB Register (Address = 0xC2) [reset = 0x0]
        1. Table 27. BIT_SAMPLE_MSB Register Field Descriptions
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Charge-Kickback Filter and ADC Amplifier
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
    1. 9.1 AVDD and DVDD Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Features

  • Small solution size:
    • 1.62-mm × 1.62-mm WCSP
    • Space-saving, capless, 2.5-V internal reference
  • 8 channels configurable as any combination of:
    • Up to 8 analog inputs, digital inputs, or digital outputs
  • Programmable averaging filters:
    • Programmable sample size for averaging
    • Averaging with internal conversions
    • 20-bit resolution for average output
  • Low-leakage multiplexer with channel sequencer:
    • Manual mode
    • On-the-fly mode
    • Auto-sequence mode
  • Excellent AC and DC performance:
    • SNR: 86 dB, THD: –100 dB
    • Improved SNR with programmable averaging filters
    • INL: ±1 LSB, 16-bit no missing codes
    • Internal calibration improves offset and drift
    • High sample rate with no latency output:
      • 250 kSPS
  • Wide operating range:
    • ADC input range: 0 V to VREF and 2 x VREF
    • Analog supply: 3 V to 5.5 V
    • Digital supply: 1.65 V to 5.5 V
    • Temperature range: –40°C to +125°C
  • Enhanced-SPI digital interface:
    • High-speed, 60-MHz SPI interface
    • Achieve full throughput with > 4.5-MHz SPI