SBAS766B May   2016  – January 2017 ADS54J20

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  AC Characteristics
    7. 7.7  Digital Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Typical Characteristics
    10. 7.10 Typical Characteristics: Contour
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Inputs
      2. 8.3.2 DDC Block
        1. 8.3.2.1 Decimate-by-2 Filter
        2. 8.3.2.2 Decimate-by-4 Filter Using a Digital Mixer
        3. 8.3.2.3 Decimate-by-4 Filter with IQ Outputs
      3. 8.3.3 SYSREF Signal
        1. 8.3.3.1 SYSREF Not Present (Subclass 0, 2)
      4. 8.3.4 Overrange Indication
        1. 8.3.4.1 Fast OVR
      5. 8.3.5 Power-Down Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration
        1. 8.4.1.1 Serial Interface
        2. 8.4.1.2 Serial Register Write: Analog Bank
        3. 8.4.1.3 Serial Register Readout: Analog Bank
        4. 8.4.1.4 JESD Bank SPI Page Selection
        5. 8.4.1.5 Serial Register Write: JESD Bank
          1. 8.4.1.5.1 Individual Channel Programming
        6. 8.4.1.6 Serial Register Readout: JESD Bank
      2. 8.4.2 JESD204B Interface
        1. 8.4.2.1 JESD204B Initial Lane Alignment (ILA)
        2. 8.4.2.2 JESD204B Test Patterns
        3. 8.4.2.3 JESD204B Frame
        4. 8.4.2.4 JESD204B Frame
        5. 8.4.2.5 JESD204B Frame Assembly with Decimation
          1. 8.4.2.5.1 JESD Transmitter Interface
          2. 8.4.2.5.2 Eye Diagrams
    5. 8.5 Register Maps
      1. 8.5.1 Detailed Register Information
      2. 8.5.2 Example Register Writes
      3. 8.5.3 Register Descriptions
        1. 8.5.3.1 General Registers
          1. 8.5.3.1.1 Register 0h (address = 0h)
          2. 8.5.3.1.2 Register 3h (address = 3h)
          3. 8.5.3.1.3 Register 4h (address = 4h)
          4. 8.5.3.1.4 Register 5h (address = 5h)
          5. 8.5.3.1.5 Register 11h (address = 11h)
        2. 8.5.3.2 Master Page (080h) Registers
          1. 8.5.3.2.1  Register 20h (address = 20h), Master Page (080h)
          2. 8.5.3.2.2  Register 21h (address = 21h), Master Page (080h)
          3. 8.5.3.2.3  Register 23h (address = 23h), Master Page (080h)
          4. 8.5.3.2.4  Register 24h (address = 24h), Master Page (080h)
          5. 8.5.3.2.5  Register 26h (address = 26h), Master Page (080h)
          6. 8.5.3.2.6  Register 4Fh (address = 4Fh), Master Page (080h)
          7. 8.5.3.2.7  Register 53h (address = 53h), Master Page (080h)
          8. 8.5.3.2.8  Register 54h (address = 54h), Master Page (080h)
          9. 8.5.3.2.9  Register 55h (address = 55h), Master Page (080h)
          10. 8.5.3.2.10 Register 59h (address = 59h), Master Page (080h)
        3. 8.5.3.3 ADC Page (0Fh) Register
          1. 8.5.3.3.1 Register 5F (addresses = 5F), ADC Page (0Fh)
        4. 8.5.3.4 Main Digital Page (6800h) Registers
          1. 8.5.3.4.1  Register 0h (address = 0h), Main Digital Page (6800h)
          2. 8.5.3.4.2  Register 41h (address = 41h), Main Digital Page (6800h)
          3. 8.5.3.4.3  Register 42h (address = 42h), Main Digital Page (6800h)
          4. 8.5.3.4.4  Register 43h (address = 43h), Main Digital Page (6800h)
          5. 8.5.3.4.5  Register 44h (address = 44h), Main Digital Page (6800h)
          6. 8.5.3.4.6  Register 4Bh (address = 4Bh), Main Digital Page (6800h)
          7. 8.5.3.4.7  Register 4Dh (address = 4Dh), Main Digital Page (6800h)
          8. 8.5.3.4.8  Register 4Eh (address = 4Eh), Main Digital Page (6800h)
          9. 8.5.3.4.9  Register 52h (address = 52h), Main Digital Page (6800h)
          10. 8.5.3.4.10 Register 72h (address = 72h), Main Digital Page (6800h)
          11. 8.5.3.4.11 Register ABh (address = ABh), Main Digital Page (6800h)
          12. 8.5.3.4.12 Register ADh (address = ADh), Main Digital Page (6800h)
          13. 8.5.3.4.13 Register F7h (address = F7h), Main Digital Page (6800h)
        5. 8.5.3.5 JESD Digital Page (6900h) Registers
          1. 8.5.3.5.1  Register 0h (address = 0h), JESD Digital Page (6900h)
          2. 8.5.3.5.2  Register 1h (address = 1h), JESD Digital Page (6900h)
          3. 8.5.3.5.3  Register 2h (address = 2h), JESD Digital Page (6900h)
          4. 8.5.3.5.4  Register 3h (address = 3h), JESD Digital Page (6900h)
          5. 8.5.3.5.5  Register 5h (address = 5h), JESD Digital Page (6900h)
          6. 8.5.3.5.6  Register 6h (address = 6h), JESD Digital Page (6900h)
          7. 8.5.3.5.7  Register 7h (address = 7h), JESD Digital Page (6900h)
          8. 8.5.3.5.8  Register 16h (address = 16h), JESD Digital Page (6900h)
          9. 8.5.3.5.9  Register 31h (address = 31h), JESD Digital Page (6900h)
          10. 8.5.3.5.10 Register 32h (address = 32h), JESD Digital Page (6900h)
        6. 8.5.3.6 JESD Analog Page (6A00h) Registers
          1. 8.5.3.6.1 Registers 12h-5h (addresses = 12h-5h), JESD Analog Page (6A00h)
          2. 8.5.3.6.2 Register 16h (address = 16h), JESD Analog Page (6A00h)
          3. 8.5.3.6.3 Register 17h (address = 17h), JESD Analog Page (6A00h)
          4. 8.5.3.6.4 Register 1Ah (address = 1Ah), JESD Analog Page (6A00h)
          5. 8.5.3.6.5 Register 1Bh (address = 1Bh), JESD Analog Page (6A00h)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Start-Up Sequence
      2. 9.1.2 Hardware Reset
      3. 9.1.3 SNR and Clock Jitter
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Transformer-Coupled Circuits
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Sequencing and Initialization
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13 Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • 12-Bit Resolution, Dual-Channel, 1-GSPS ADC
  • Noise Floor: –157 dBFS/Hz
  • Spectral Performance (fIN = 170 MHz at –1 dBFS):
    • SNR: 67.8 dBFS
    • NSD: –155 dBFS/Hz
    • SFDR: 86 dBc (Including Interleaving Tones)
    • SFDR: 89 dBc (Except HD2, HD3, and Interleaving Tones)
  • Spectral Performance (fIN = 350 MHz at –1 dBFS):
    • SNR: 65.6 dBFS
    • NSD: –152.6 dBFS/Hz
    • SFDR: 75 dBc
    • SFDR: 85 dBc (Except HD2, HD3, and Interleaving Tones)
  • Channel Isolation: 100 dBc at fIN = 170 MHz
  • Input Full-Scale: 1.9 VPP
  • Input Bandwidth (3 dB): 1.2 GHz
  • On-Chip Dither
  • Integrated Wideband DDC Block
  • JESD204B Interface with Subclass 1 Support:
    • 2 Lanes per ADC at 10.0 Gbps
    • 4 Lanes per ADC at 5.0 Gbps
    • Support for Multi-Chip Synchronization
  • Power Dissipation: 1.35 W/Ch at 1 GSPS
  • Package: 72-Pin VQFNP (10 mm × 10 mm)

2 Applications

  • Radar and Antenna Arrays
  • Broadband Wireless
  • Cable CMTS, DOCSIS 3.1 Receivers
  • Communications Test Equipment
  • Microwave Receivers
  • Software Defined Radios (SDRs)
  • Digitizers
  • Medical Imaging and Diagnostics

3 Description

The ADS54J20 is a low-power, wide-bandwidth, 12-bit, 1.0-GSPS, dual-channel, analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device delivers a noise floor of –157 dBFS/Hz for applications aiming for highest dynamic range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with data rates up to 10 Gbps, supporting two or four lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. Optionally, each ADC channel can be connected to a wideband digital down-converter (DDC) block. The ADS54J20 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption.

The JESD204B interface reduces the number of interface lines, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the ADC sampling clock to derive the bit clock that is used to serialize the 12-bit data from each channel.

Device Information

PART NUMBER PACKAGE BODY SIZE (NOM)
ADS54J20 VQFNP (72) 10.00 mm × 10.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

FFT for 170-MHz Input Signal

ADS54J20 D000_SBAS766.gif

4 Revision History

Changes from A Revision (May 2016) to B Revision

  • Changed the Device Comparison TableGo
  • Added the FOVR latency parameter to the Timing Characteristics tableGo
  • Added SYSREF Not Present (Subclass 0, 2) sectionGo
  • Changed the number of clock cycles in the Fast OVR sectionGo
  • Changed the Register MapGo
  • Deleted register 39h, 3Ah, and 56h Go
  • Changed Power Supply Recommendations section Go
  • Added the Power Sequencing and Initialization sectionGo
  • Added the Receiving Notification of Documentation Updates sectionGo

Changes from * Revision (May 2016) to A Revision

  • Released to production Go