SBAS840A July   2020  – September 2020 ADC3541

ADVANCE INFORMATION  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Descriptions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications
    8. 6.8  Timing Requirements
    9. 6.9  Typical Characteristics
    10. 6.10 Parameter Measurement Information
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
        1. 7.3.1.1 Analog Input Bandwidth
        2. 7.3.1.2 Analog Front End Design
          1. 7.3.1.2.1 Sampling Glitch Filter Design
          2. 7.3.1.2.2 Single Ended Input
          3. 7.3.1.2.3 Analog Input Termination and DC Bias
            1. 7.3.1.2.3.1 AC-Coupling
            2. 7.3.1.2.3.2 DC-Coupling
        3. 7.3.1.3 Auto-Zero Feature
      2. 7.3.2 Clock Input
        1. 7.3.2.1 Single Ended vs Differential Clock Input
        2. 7.3.2.2 Signal Acquisition Time Adjust
      3. 7.3.3 Voltage Reference
        1. 7.3.3.1 Internal voltage reference
        2. 7.3.3.2 External voltage reference (VREF)
        3. 7.3.3.3 External voltage reference with internal buffer (REFBUF)
      4. 7.3.4 Digital Down Converter
        1. 7.3.4.1 Digital Filter Operation
        2. 7.3.4.2 Numerically Controlled Oscillator (NCO) and Digital Mixer
        3. 7.3.4.3 Decimation Filter
        4. 7.3.4.4 SYNC
        5. 7.3.4.5 Output Formatting with Decimation
          1. 7.3.4.5.1 Parallel CMOS
          2. 7.3.4.5.2 Serialized CMOS Interface
      5. 7.3.5 Digital Interface
        1. 7.3.5.1 Parallel CMOS Output
        2. 7.3.5.2 Serialized CMOS output
          1. 7.3.5.2.1 SDR Output Clocking
        3. 7.3.5.3 Output Data Format
        4. 7.3.5.4 Output Formatter
        5. 7.3.5.5 Output Interface/Mode Configuration
          1. 7.3.5.5.1 Configuration Example
      6. 7.3.6 Test Pattern
      7. 7.3.7 Temperature Sensor
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal operation
      2. 7.4.2 Power Down Options
    5. 7.5 Programming
      1. 7.5.1 Configuration using PINs only
      2. 7.5.2 Configuration Using the SPI Interface
        1. 7.5.2.1 Register Write
        2. 7.5.2.2 Register Read
    6. 7.6 Register Map
      1. 7.6.1 Detailed Register Description
  8. Application and Implementation
    1. 8.1 Typical Application
      1. 8.1.1 Design Requirements
      2. 8.1.2 Detailed Design Procedure
        1. 8.1.2.1 Input Signal Path
        2. 8.1.2.2 Sampling Clock
        3. 8.1.2.3 Voltage Reference
      3. 8.1.3 Application Curves
    2. 8.2 Initialization Set Up
      1. 8.2.1 Register Initialization
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Support Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Features

  • 14-bit 10/25/65 MSPS ADC
  • Noise floor: –155 dBFS/Hz
  • Ultra-low power with optimized power scaling:
    36 mW (10 MSPS) to 79 mW (65 MSPS)
  • Latency: 1 clock cycle
  • INL: ±0.5 LSB; DNL: ±0.05 LSB
  • Reference: external or internal
  • Input Bandwidth: 400 MHz (3-dB)
  • Industrial temperature range: –40°C to +105°C
  • On-chip digital filter (optional)
    • Decimation by 2, 4, 8, 16, 32
    • 32-bit NCO
  • SDR/DDR and Serial CMOS interface
  • Small footprint: 40-VQFN (5 mm × 5 mm) package
  • Single 1.8-V supply
  • Spectral Performance (fIN = 10 MHz):
    • SNR: 79.0 dBFS
    • SFDR: 90 dBc HD2, HD3
    • SFDR: 100 dBFS Worst Spur
  • Spectral Performance (fIN = 70MHz):
    • SNR: 75.0 dBFS
    • SFDR: 70 dBc HD2, HD3
    • SFDR: 90 dBFS Worst Spur