[JINGLE] Hello, and welcome to the multiplexer series on basics of multiplexers and signal switches. This video series explains basics of analog signal switches offered by Texas Instruments. 

In this video, we will first have a short discussion on the difference between an analog and digital signal switch. Next, we will discuss the basic construction of common analog switches. Specifically, we will see how on-resistance varies with the input signals for different types of switches. The goal of this video is to understand how analog switches differ from digital switches and the common TI analog and digital switch architectures. 

An analog switch is designed to support analog signals such as audio and sensor inputs. These switches often exhibit good digital signal performance as well. A digital or a bus switch is designed to pass or isolate digital signal levels. These switches may exhibit the capability to satisfactorily passing analog signals as well. 

TI's analog and digital bus switches and multiplexers are electrically equivalent, and both share the common switch architectures found in the semiconductor industry. Signal switches in their simplest form are MOSFET structures with the gate driven by a CMOS inverter. The most common and widely used switch types are NFET switches, transmission gate switches, and NFET with charge pump. Let's take a look at the basic construction of these switches and understand their key characteristics. 

This slide shows the typical construction of a simplified FET switch which consists of an N-channel transistor, gate bias, and enables circuitry. The switch is bi-directional, meaning the source and the drain are interchangeable. The terminal with the lowest voltage is considered to be the source. 

The resistance r on between the drain and the source depends on the voltage difference between the gate and the source, VGS. When there is sufficient voltage applied to the gate with respect to the source, the switch becomes conductive, and a voltage signal applied to the drain passes through the switch without distortion. 

The gate-to-source voltage at which the NMOS begins conduction is known as the threshold voltage, VT. Then the output enable-- OE-- signal is low, the voltage at the gate is high or equal to VCC. If the voltage at the drain, VI, is less than VCC by the threshold voltage of the N-channel transistor, the on-resistance is low and the voltage at the source is equal to VI. 

If VI approaches VCC, r on increases rapidly. The source voltage does not increase with the drain voltage, and the output voltage remains at VCC minus VT. The r on versus VI curve shows the general shape of r on vs. VI characteristics of a typical NMOS series switch. 

The N-channel FET switch is simple and can be used as a translator if the I/O pin goes above supply. A limitation of the NMOS series switch is that it can pass signals only up to a threshold voltage below VCC. 

The slide here shows the typical construction of a parallel NMOS/PMOS FET switch, also known as the transmission gate switch. An NMOS/PMOS parallel switch consists of an N-channel pass transistor in parallel with a P-channel pass transistor. In an N-channel MOSFET, the source-to-drain resistance is low when the drain voltage is less than VG minus VT, where VG is the gate voltage. In a P-channel MOSFET, the source-to-drain resistance is low when the source voltage is greater than VT plus VG. 

With the parallel combination of N channel and P channel path transistors, the source-to-drain or the channel resistance can be lowered for the entire input voltage range from 0 volt to VG. This resulting parallel resistance combination is much flatter than individual N- and P-channel resistances. A flat r on is especially important if V I/O signals must swing from rail to rail. When enable OE is low, VG in NMOS/PMOS parallel switch is VCC, and signals ranging from 0 volt to VCC can be passed through the switch. 

The graph shows the general shape of the r on versus VI characteristics of a typical NMOS/PMOS parallel switch, as well as the NMOS and PMOS characteristics. The shape of r on versus VI curve may be different depending on the structures of NMOS and PMOS. The disadvantage of NMOS/PMOS parallel switch is that the input and output capacitance is increased due to the additional source and drain area of the combined transistor. 

The slide here shows the typical construction of an NMOS switch with charge pump. Although in a transmission gate switch, the source-to-drain resistance is lower than an N-channel FET switch, the PMOS adds capacitance, which is undesirable for some applications. To solve this problem, another type of switch structure is used that involves a charge from circuit in the NMOS series switch. 

The charge pump circuit generates a voltage at the gate of the NMOS that is two to three volts higher than VCC. As a result, when the input reaches the VCC level, the switch still is on, and the output voltage is equal to the input voltage over the 0 to VCC input voltage range. 

The graph shows the r on vs. Input voltage characteristics of an N channel FET switch with the charge pump. The disadvantage of implementing a charge pump circuit in an NMOS series switch is in the additional power consumption because of the charge pump circuit. 

Thank you for watching the TI precision lab video, "What are common switch architectures?" To find more switches and multiplexers, technical resources, and search products, visit ti.com