Here's a summary of the layout variables that were evaluating to test how layout affects the thermal performance of a HotRod package IC. The first variable change was the copper dimensions of the PCB. The copper dimensions were swept from three inches by three inches down to one inch by one inch. 

So we would expect that with a larger copper area, there is a larger area to conduct the heat away from the IC. So the thermal performance will be better. But this will quantify how much. 

Next what was varied was via rules. Minimum via rules depends on the PCB fab shop that's being used to fab the PCBs. So there are three different parameters of the via that were varied here. The three were the hole size, which is the actual drill hole of the IC. And that's shown by the image in the top right. 

The next was the pad of the IC. This is typically given by the rule of the minimum annular ring. The rule used in this case was a six mil annular ring. At least for this 12 mil hole, it was a six mil annular ring. So this gave a 12 mil hole and a 24 mil capture pad for the via. 

The next rule is the spacing in the vias. And for this one, the rule was 20 mil hole to hole. The via rules were varied to show the difference between a relatively lower cost process and a relatively higher cost process. So typically, a larger via with a larger capture pad is a lower cost process. And a smaller via with a smaller capture pad is a higher cost process. 

The other thing that can increase costs is the number of vias. So a higher via density will have a higher cost. So the 12 mil hole, 24 mil is probably more of a standard size. And same for the 10 mil hole, 22 mil. It's a relatively standard size. Just a slightly smaller via hole size. 

The 10 mil hole and 30 mil pad is a much lower cost size and spacing as a 45 mil hole-to-hole spacing. And this was actually sized so that you could fit a 10 mil trace between the vias, which could be advantageous in certain applications. So you don't want the vias to get in the way of other routing. 

And then this last one is a relatively more expensive process, where it has smaller vias with a lot tighter spacing. So you have a much higher via count. Along with these rules, the via count was also varied to see how the via count affects the thermal performance of the HotRod package. 

The two variables that were unchanged, but it should be mentioned because they do significantly affect thermal performance, is the layer count of the PCB and the copper weight of the PCB. So in this case, all the layouts were four layers with two ounce copper on all four layers. 

Here's the full layout for the PCB that was the initial design that generated all these different layouts. So here on the left is the top layer. On the top layer, we have traces for PGND, VIN, and VOUT, and a separate area for AGND. So there's power routing on here, and the PGND area is maximized. 

The mid-layer one, or second layer, is all filled in with PGND. This is done for two reasons. First, this big layer is closest to the top layer, closest to the IC package. So it's a good way for heat to conduct out of the IC and then spread onto this entire layer. The other reason is this IC has PGND pins on both sides. 

And it's important to have low inductance between the two sides of the IC to improve the switching performance of the IC. This will keep the noise low and reduce ringing on the switching node. There's a couple of other traces on here. And they're just routing to test points on the PCB. 

The next layer is mostly PGND. but it also has parallel planes for VIN and VOUT to reduce the resistance of these planes. For the VIN, this is also needed, because, like the PGND, there is VIN on both sides of this IC. And you need a VIN copper area to connect these two sides of the IC. 

The other trace on here is for the BOOTPIN. This is kept on this layer, so it doesn't break up the PGND layer on Layer 2 or Layer 1. And then lastly is the bottom layer. This layer is mostly PGND, again, to help to maximize the PGND area to aid with convection. This also, again, spreads the heat and improves thermal performance. The other trace on here is the trace from VOUT from the feedback divider of the IC. 

The first layouts tested is for this experiment were layouts of the released EVM for this IC. So these EVMS use a three inch by three inch copper area. And there has been one revision to this EVM since its release. 

On the left is the initial revision, where you could say there are six vias for thermal performance. But in reality, it may only be two vias that are very effective. Because as the vias get further away from the package, the effectiveness of the vias to aid in internal performance becomes less. 

On the right, we added a couple of more vias that are in good locations to aid with the thermal performance. It's these two vias that are between the PGND pins of the IC and the input capacitors. They're right next to the IC, and they can really help with thermal performance. 

The other thing that was changed is the boot cap was moved, so that we can maximize the PGND copper next to the IC on the top layer. This one, I'm saying it has 10 vias for thermal performance. It has five on each side. So what you can see from this is that theta JA was improved pretty significantly by adding these vias to improve the thermal performance. So it went from 25 degrees C per watt down to 22.3 degrees C per watt, which is pretty good. 

The other thing I should mention here is the theta JA numbers given were measured using the controlled IC power dissipation method, where the input voltage was reverse. And the actual power dissipation in the IC was forced and measured. This was used for comparing the layouts, because it's more controlled. You can give a more accurate comparison. 

The next comparison being done is between different via rules and number of vias. All of these layouts used a two inch by two inch copper area. So this first one on the top left, I'm calling a typical via density. And this one, you could say, has 10 vias on each side. 

There are eight vias total that are right next to the package that aide in the thermal performance. This next one to the right, I'm calling a low via density, where there's six PGND thermal vias on each side. 

The vias are widely spaced, so that you can actually fit a trace between the vias. You might say this is actually four vias. But since I'm enclosing six vias to count for this one. 

This one on the bottom left is the same as a typical via density. But I've just added two more vias on each side to see how adding these vias will affect the thermal performance. And lastly, the one on the bottom right has a higher via density with smaller vias. So this one has actually a total of 20 vias to help transfer heat from the top side of the board to the bottom side of the board. 

And as you can see from these theta JA numbers, there wasn't much of a difference between these layouts. And the reason for this is likely because adding more vias that are further away from the IC are not as effective. What's important is having a couple of vias near the IC to transfer the heat to internal layers and to the bottom layers. 

The other thing I want to point out with these via patterns is it's important not to block the return path between the PGND pins and the PGND pad of the input capacitors. This could add parasitic inductance between the input capacitors and the PGND and affect the switch node ringing of the IC. 

So if you look at the top left one, there's a space between the middle PGND pin and the PGND pad of the capacitors. And if you look at the bottom right, the spacing was not as tight next to the IC to make sure that the inductance between the IC and the input caps was not increased. 

The other reason for this difference is that the smaller vias have a much higher thermal resistance. So even though there's more eight mil vias in the higher density layout, the thermal resistance really isn't that much lower than the typical thermal resistance, where we've added some vias. 

So on this table on the right, I've used this equation to calculate the thermal resistance of a single via and the thermal resistance of all the vias in parallel. A couple of things about this assumption really is that this assumes that each thermal via is equally as effective at transferring heat from the IC to the internal layers and the bottom layers. But in reality, as vias get further away from the IC, they're less effective at transferring heat. They don't improve the thermal performance as much. 

The other thing is these thermal resistances are the thermal resistance from the top layer of the PCB to the bottom layer of the PCB, given by the length of 62 mils. But again, heat is transferred not only from the top and the bottom, but also from the top of the PCB to internal layers of the PCB. So in the end, it is more cost effective to use a larger 12 mil via and less of them versus having a smaller 8 mil via and a lot of them to get the same thermal resistance. 

The other thing that comes up a lot is you might want to put a via in the pad or between the pads and the IC to help with the thermal performance. But unfortunately, with this IC, the size of the VIN pins and the spacing of the pins do not allow this. So the VIN pins, their width is actually approximately 16 mil. So if you use that smaller 8 mil vias with a 16 mil capture pad, they would technically fit. And they could be used. 

But the issue is with a VIN pad, it can wick solder away and affect the solder contact between the IC and the PCB. This would hurt the switching performance and potentially the thermal performance of the IC. Because it's not making as much of a contact. 

To get vias between the pins of the IC, you'd have to have the entire capture pad of the via to fit between. So the 16 mil via does not fit in this 12 mil spacing. And the issue is the PCB fab process is not accurate enough to make sure this via always falls between the two pins at the IC. 

The other thing to mention is if you put a via in the VIN pin, you could fill it. But the trade-off is this adds costs to the via. It'll help thermal performance. But it doesn't come for free. 

With all of these considerations in mind, there was a footprint experiment that was also tested. So if you look at the left, we have a typical via density, where we had five vias on each side. And on the right, we did this experiment where we put some vias underneath the package. And this does actually follow the rules. 

The way that this was done is if you look at the darker gray, this is the solder mask opening on the PCB. So what we've done is the solder mask opening does not cover the entire pin of the IC. It's a little bit smaller, which allows us to put these four vias underneath the IC. They're not at risk of wicking away solder to reduce the electrical contact of the IC to the PCB. 

But the result of this was actually worse thermal performance. It went from 28 degrees C per watt up to almost 30 degrees C per watt. And the most likely reason for this is now there is less metal contact between the IC and the PCB. 

This actually increases the thermal resistance between the IC and the PCB, even though it might improve the thermal resistance from the top layer of the PCB to the bottom layer of the PCB. So again, the net effect is actually worse thermal performance. And having more metal contact between the IC and the PCB was more important. 

The last thing evaluated was an even smaller copper area of one inch by one inch. And in these images below show the comparison of the two inch by two inch layout and the one inch by one inch layout. So as can be expected, with the one inch by one inch layout, the theta JA went up. It went up to 33 degrees C per watt from 28 degrees C per watt. 

And if you look at this, the size of the one inch by one inch layout, it's about the right copper area needed to cover all the components needed for the TPS 54824 circuit. So again, smaller copper area hurts thermal performance. And that's because there's less copper area to aid in convection to transfer heat from the PCB into the ambient air. 

Here's a thermal image that shows how the thermal gradient is different between the different sized copper areas. So on the left is a three inch by three inch. In the middle is a two inch by two inch. And the right, the one inch by one inch. 

And with these thermal images, the case temperature on the three inch by three inch is 60.3 degrees C. On the two inch by two inch, 68.0 degrees C. And on the one inch by one inch, 75.3 degrees C. There's about a seven to eight degrees C increase from the larger copper area to the smaller copper area. 

The other interesting thing you can see from these pictures is you can see the edge of the copper area on the image. The actual PCB size was still three inches by three inches. Just the copper area was limited to two inch by two inch or one inch by one inch. You can see the edge of the copper is much hotter with a smaller copper area. And there's a really steep thermal gradient from the edge of the copper into the PCB once you get to the edge of the copper. 

Finally, here's a table that summarizes the results from all these experiments. Each layout is ordered from best thermal performance to worst thermal performance. And they are ranked by the theta JA measurement with the power loss in the IC only. So that is the second column is the theta JA with power loss in the IC only. 

The third column is theta JA when the IC is operating as a power supply, where again, the power loss of the inductor had to be subtracted out to get the actual power dissipation in the IC. So again, you can see that the Rev B EVM with the extra vias has the best thermal performance. The Rev A EVM has better thermal performance than the other via patterns mostly because it has a larger three inch by three inch copper area. 

Then if you look at the four via pattern experiments, they're all about the same. They're pretty much within the measurement error or maybe the variation in the IC or in the PCB fab. Again, the footprint experiment is the same as these four. 

And then lastly, the worst is the one inch by one inch copper area. This just stresses the importance of maximizing the copper area to spread the heat away from the IC to aid in the thermal performance. 

And lastly, here are some of the recommended best practices. I'm going to do a layout for a HotRod packaged IC. A lot of these will also apply to a regular QFN IC. But some of them are specific to just the HotRod only. 

So the first point is that adding more than 6 vias had little effect. It's more important to have a few well-placed large vias and place them as close as possible to the package as is practical. This is what's most important when you're really trying to optimize the via pattern for the IC. 

The next is that maximizing the ground copper area is very critical for heat to flow from the IC. This had the largest effect in all of the experiments that were run. Next is you need to be careful about placing too many vias, so that you're not cutting up the thermal path or adding inductance between the pins of the IC and the bypass capacitors. This could add noise to the switching node and affect the actual performance of the IC. 

The other points are since there's low thermal resistance between the IC and all of its pins, you can use the other pins of the IC to help conduct heat away from the IC and improve thermal performance. So the first one is the VIN copper, because it's typically a larger plane. Because you have typically higher current. So you can maximize the copper connected to this pin to help provide another path of heat to flow from the IC. 

Next, the thermal coupling to the inductor is very important as mentioned earlier. So if you have a hot inductor, it is very tightly thermal coupled to the IC through the switching node. Lastly, the VOUT copper, since there's a tight coupling between the inductor and the IC, the VOUT copper can actually also help with the thermal performance of the inductor. So if you can use the VOUT copper to cool down the inductor, it could actually cool down the IC as well.