THS8200

正在供货

三通道 10 位全格式视频 DAC

产品详情

Rating Catalog Operating temperature range (°C) 0 to 70
Rating Catalog Operating temperature range (°C) 0 to 70
HTQFP (PFP) 80 196 mm² 14 x 14
  • Overall
    • Three 11-Bit 205-MSPS Digital-to-Analog Converters (DACs) With Integrated Bi-Level or Tri-Level Sync Insertion
    • Support for All ATSC Video Formats (Including 1080P) and PC Graphics Formats (up to UXGA at 75 Hz)
  • Input
    • Flexible 10-, 15-, 16-, 20-, 24-, or 30-Bit Digital Video Input Interface With Support for YCbCr or RGB Data, Either 4:4:4 or 4:2:2 Sampled
    • Video Synchronization by Hsync or Vsync Dedicated Inputs or by Extraction of Embedded SAV and EAV Codes According to ITU-R.BT601 (SDTV) or SMPTE 274M and SMPTE 296M (HDTV)
    • Glueless Interface to TI DVI 1.0 (With HDCP) Receivers. Can Receive Video-Over-DVI Formats According to the EIA-861 Specification and Convert to YPbPr or RGB Component Formats With Separate Syncs or Embedded Composite Sync.
  • Video Processing
    • Programmable Clip/Shift/Multiply Function for Operation With Full-Range or ITU-R.BT601 Video Range Input Data
    • Programmable Digital Fine-Gain Controller on Each Analog Output Channel, for Accurate Channel Matching and Programmable White-Balance Control
    • Built-In 4:2:2 to 4:4:4 Video Interpolation Filter
    • Built-In 2x Oversampling SDTV and HDTV Interpolation Filter for Improved Video Frequency Characteristic
    • Fully Programmable Digital Color Space Conversion Circuit
    • Fully Programmable Display Timing Generator to Supply All SDTV and HDTV Composite Sync Timing Formats, Progressive and Interlaced
    • Fully Programmable Hsync and Vsync Outputs
    • Vertical Blanking Interval (VBI) Override or Data Pass-Through for VBI Data Transparency
    • Programmable CGMS Data Generation and Insertion
  • Output
    • Digital
      • ITU-R BT.656 Digital Video Output Port
    • Analog
      • Analog Component Output from Software-Switchable 700-mV or 1.3-V Compliant Output DACs at 37.5-Ω Load
      • Programmable Video/Sync Ratio (7:3 or 10:4)
      • Programmable Video Pedestal
  • General
    • Built-In Video Color Bar Test Pattern Generator
    • Fast Mode I2C Control Interface
    • Configurable Master or Slave Timing Mode
      • Configuration Modes Allow the Device to Act as a Master Timing Source for Requesting Data From, for Example, the Video Frame Buffer (Master Mode Only Available for PC Graphics Output Modes).
      • Alternatively, the Device Can Slave to an External Timing Master.
    • DAC and Chip Power-Down Modes
    • Low-Power 1.8-V and 3.3-V Operation
    • 80-Pin PowerPAD Plastic Quad Flatpack Package With Efficient Heat Dissipation and Small Physical Size
  • Overall
    • Three 11-Bit 205-MSPS Digital-to-Analog Converters (DACs) With Integrated Bi-Level or Tri-Level Sync Insertion
    • Support for All ATSC Video Formats (Including 1080P) and PC Graphics Formats (up to UXGA at 75 Hz)
  • Input
    • Flexible 10-, 15-, 16-, 20-, 24-, or 30-Bit Digital Video Input Interface With Support for YCbCr or RGB Data, Either 4:4:4 or 4:2:2 Sampled
    • Video Synchronization by Hsync or Vsync Dedicated Inputs or by Extraction of Embedded SAV and EAV Codes According to ITU-R.BT601 (SDTV) or SMPTE 274M and SMPTE 296M (HDTV)
    • Glueless Interface to TI DVI 1.0 (With HDCP) Receivers. Can Receive Video-Over-DVI Formats According to the EIA-861 Specification and Convert to YPbPr or RGB Component Formats With Separate Syncs or Embedded Composite Sync.
  • Video Processing
    • Programmable Clip/Shift/Multiply Function for Operation With Full-Range or ITU-R.BT601 Video Range Input Data
    • Programmable Digital Fine-Gain Controller on Each Analog Output Channel, for Accurate Channel Matching and Programmable White-Balance Control
    • Built-In 4:2:2 to 4:4:4 Video Interpolation Filter
    • Built-In 2x Oversampling SDTV and HDTV Interpolation Filter for Improved Video Frequency Characteristic
    • Fully Programmable Digital Color Space Conversion Circuit
    • Fully Programmable Display Timing Generator to Supply All SDTV and HDTV Composite Sync Timing Formats, Progressive and Interlaced
    • Fully Programmable Hsync and Vsync Outputs
    • Vertical Blanking Interval (VBI) Override or Data Pass-Through for VBI Data Transparency
    • Programmable CGMS Data Generation and Insertion
  • Output
    • Digital
      • ITU-R BT.656 Digital Video Output Port
    • Analog
      • Analog Component Output from Software-Switchable 700-mV or 1.3-V Compliant Output DACs at 37.5-Ω Load
      • Programmable Video/Sync Ratio (7:3 or 10:4)
      • Programmable Video Pedestal
  • General
    • Built-In Video Color Bar Test Pattern Generator
    • Fast Mode I2C Control Interface
    • Configurable Master or Slave Timing Mode
      • Configuration Modes Allow the Device to Act as a Master Timing Source for Requesting Data From, for Example, the Video Frame Buffer (Master Mode Only Available for PC Graphics Output Modes).
      • Alternatively, the Device Can Slave to an External Timing Master.
    • DAC and Chip Power-Down Modes
    • Low-Power 1.8-V and 3.3-V Operation
    • 80-Pin PowerPAD Plastic Quad Flatpack Package With Efficient Heat Dissipation and Small Physical Size

The THS8200 device is a complete video back-end D/A solution for DVD players, personal video recorders and set-top boxes, or any system requiring the conversion of digital component video signals into the analog domain.

The THS8200 device can accept a variety of digital input formats, in 4:4:4 and 4:2:2 formats, over an interface of three, two, or one 10‑bit ports. The device synchronizes to incoming video data either through dedicated Hsync and Vsync inputs or through extraction of the sync information from embedded sync (SAV and EAV) codes inside the video stream. Alternatively, when the THS8200 is configured for generating PC graphics output, the device also provides a master timing mode in which it requests video data from an external (memory) source.

The THS8200 device contains a display timing generator that is completely programmable for all standard and nonstandard video formats up to the maximum supported pixel clock of 205 MSPS. Therefore, the device supports all component video and PC graphics (VESA) formats. A fully programmable 3x3 matrixing operation is included for color space conversion. All video formats, up to the HDTV 1080I and 720P formats, can also be internally 2x oversampled. Oversampling relaxes the need for sharp external analog reconstruction filters behind the DAC and improves the video frequency characteristic.

The output compliance range can be set through external adjustment resistors, and there is a choice of two settings to accommodate both component video or PC graphics (700-mV) and composite video (1.3‑V) outputs without hardware changes. An internal programmable clip/shift/multiply function on the video data assures standards-compliant video output ranges for either full 10-bit or reduced ITU-R.BT601 style video input. To avoid nonlinearities after scaling of the video range, the DACs have 11-bit resolution internally. Furthermore, a bi-level or tri-level sync with programmable amplitude (to support both 700-mV:300-mV and 714-mV:286-mV video:sync ratios) can be inserted either on the green/luma channel only or on all three output channels. This sync insertion is generated from additional current sources in the DACs such that the full DAC resolution remains available for the video range and preserves 100% of the 11-bit dynamic range of the DAC for video data.

The THS8200 optionally supports the pass-through of ancillary data embedded in the input video stream or can insert ancillary data into the 525P analog component output according to the CGMS data specification.

The THS8200 device is a complete video back-end D/A solution for DVD players, personal video recorders and set-top boxes, or any system requiring the conversion of digital component video signals into the analog domain.

The THS8200 device can accept a variety of digital input formats, in 4:4:4 and 4:2:2 formats, over an interface of three, two, or one 10‑bit ports. The device synchronizes to incoming video data either through dedicated Hsync and Vsync inputs or through extraction of the sync information from embedded sync (SAV and EAV) codes inside the video stream. Alternatively, when the THS8200 is configured for generating PC graphics output, the device also provides a master timing mode in which it requests video data from an external (memory) source.

The THS8200 device contains a display timing generator that is completely programmable for all standard and nonstandard video formats up to the maximum supported pixel clock of 205 MSPS. Therefore, the device supports all component video and PC graphics (VESA) formats. A fully programmable 3x3 matrixing operation is included for color space conversion. All video formats, up to the HDTV 1080I and 720P formats, can also be internally 2x oversampled. Oversampling relaxes the need for sharp external analog reconstruction filters behind the DAC and improves the video frequency characteristic.

The output compliance range can be set through external adjustment resistors, and there is a choice of two settings to accommodate both component video or PC graphics (700-mV) and composite video (1.3‑V) outputs without hardware changes. An internal programmable clip/shift/multiply function on the video data assures standards-compliant video output ranges for either full 10-bit or reduced ITU-R.BT601 style video input. To avoid nonlinearities after scaling of the video range, the DACs have 11-bit resolution internally. Furthermore, a bi-level or tri-level sync with programmable amplitude (to support both 700-mV:300-mV and 714-mV:286-mV video:sync ratios) can be inserted either on the green/luma channel only or on all three output channels. This sync insertion is generated from additional current sources in the DACs such that the full DAC resolution remains available for the video range and preserves 100% of the 11-bit dynamic range of the DAC for video data.

The THS8200 optionally supports the pass-through of ancillary data embedded in the input video stream or can insert ancillary data into the 525P analog component output according to the CGMS data specification.

下载 观看带字幕的视频 视频

TI 不提供设计支持

TI 不会为该产品的新工程(例如新内容或软件更新)提供持续的设计支持。如可用,您将在产品文件夹中找到相关的配套资料、软件和工具。您也可以在 TI E2ETM 支持论坛中搜索已归档的信息。

技术文档

star =有关此产品的 TI 精选热门文档
未找到结果。请清除搜索并重试。
查看全部 5
类型 标题 下载最新的英语版本 日期
* 数据表 THS8200 All-Format Oversampled Component Video/PC Graphics D/A System With Three 11-Bit DACs, CGMS Data Insertion 数据表 (Rev. E) PDF | HTML 2014年 9月 18日
应用手册 THS8200 PCB Layout Guidelines 2010年 6月 16日
应用手册 Noise Analysis for High Speed Op Amps (Rev. A) 2005年 1月 17日
应用手册 使用 DM642 DSP 和 THS8200 驱动器的高分辨率视频 (Rev. A) 2004年 5月 3日
应用手册 Analog Reconstruction Filter for HDTV Using THS8133, THS8134, THS8135, THS8200 2001年 9月 14日

设计和开发

如需其他信息或资源,请点击以下任一标题进入详情页面查看(如有)。

软件编程工具

SLEC026 THS8200 Setup Files

支持的产品和硬件

支持的产品和硬件

产品
HDMI、DisplayPort 和 MIPI IC
THS8200 三通道 10 位全格式视频 DAC
支持软件

SLEC029 TVP7002 + THS8200 EVM Kit Setup

支持的产品和硬件

支持的产品和硬件

产品
HDMI、DisplayPort 和 MIPI IC
THS8200 三通道 10 位全格式视频 DAC TVP7002 三路 8/10 位 165/110MSPS 视频 ADC TVP70025I 具有水平 PLL 的三路 10 位 90MSPS 视频和图形数字转换器
模拟工具

PSPICE-FOR-TI — 适用于 TI 设计和模拟工具的 PSpice®

PSpice® for TI 可提供帮助评估模拟电路功能的设计和仿真环境。此功能齐全的设计和仿真套件使用 Cadence® 的模拟分析引擎。PSpice for TI 可免费使用,包括业内超大的模型库之一,涵盖我们的模拟和电源产品系列以及精选的模拟行为模型。

借助 PSpice for TI 的设计和仿真环境及其内置的模型库,您可对复杂的混合信号设计进行仿真。创建完整的终端设备设计和原型解决方案,然后再进行布局和制造,可缩短产品上市时间并降低开发成本。

在 PSpice for TI 设计和仿真工具中,您可以搜索 TI (...)
模拟工具

TINA-TI — 基于 SPICE 的模拟仿真程序

TINA-TI 提供了 SPICE 所有的传统直流、瞬态和频域分析以及更多。TINA 具有广泛的后处理功能,允许您按照希望的方式设置结果的格式。虚拟仪器允许您选择输入波形、探针电路节点电压和波形。TINA 的原理图捕获非常直观 - 真正的“快速入门”。

TINA-TI 安装需要大约 500MB。直接安装,如果想卸载也很容易。我们相信您肯定会爱不释手。

TINA 是德州仪器 (TI) 专有的 DesignSoft 产品。该免费版本具有完整的功能,但不支持完整版 TINA 所提供的某些其他功能。

如需获取可用 TINA-TI 模型的完整列表,请参阅:SpiceRack - 完整列表 

需要 HSpice (...)

用户指南: PDF
英语版 (Rev.A): PDF
封装 引脚 下载
HTQFP (PFP) 80 查看选项

订购和质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息:
  • 制造厂地点
  • 封装厂地点

推荐产品可能包含与 TI 此产品相关的参数、评估模块或参考设计。

支持和培训

视频