This single positive edge triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
This device is fully specified for partial power down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
(1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
|VCC (Min) (V)|
|VCC (Max) (V)|
|Voltage (Nom) (V)|
|F @ Nom Voltage (Max) (Mhz)|
|ICC @ Nom Voltage (Max) (mA)|
|tpd @ Nom Voltage (Max) (ns)|
|IOL (Max) (mA)|
|Operating Temperature Range (C)|
|Package Size: mm2:W x L (PKG)|
|D-Type Flip-Flop||D-Type Flip-Flop||D-Type Flip-Flop|
|HiRel Enhanced Product||Catalog||Automotive|
|-55 to 125||
-40 to 125
-40 to 85
|-40 to 125|
|8VSSOP: 6 mm2: 3.1 x 2(VSSOP)||
See datasheet (DSBGA)
8SM8: 12 mm2: 4 x 2.95(SM8)
8VSSOP: 6 mm2: 3.1 x 2(VSSOP)
|8VSSOP: 6 mm2: 3.1 x 2(VSSOP)|