SN74LVC2G74-EP 具有清零和预设功能的增强型产品单路上升沿 D 类触发器 | 德州仪器 TI.com.cn

SN74LVC2G74-EP (正在供货)

具有清零和预设功能的增强型产品单路上升沿 D 类触发器

具有清零和预设功能的增强型产品单路上升沿 D 类触发器 - SN74LVC2G74-EP
数据表
 

描述

This single positive edge triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.

A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

This device is fully specified for partial power down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

特性

  • Controlled Baseline
    • One Assembly Site
    • One Test Site
    • One Fabrication Site
  • Extended Temperature Performance of –55°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree(1)
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 7.9 ns at 3.3 V
  • Low Power Consumption, 10 µA Max ICC
  • ±24 mA Output Drive at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Partial Power Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

(1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

查看更多内容

参数 与其它产品相比 小尺寸逻辑产品

 
Technology Family
Sub-Family
Gate Type
VCC (Min) (V)
VCC (Max) (V)
Bits (#)
Voltage (Nom) (V)
F @ Nom Voltage (Max) (Mhz)
ICC @ Nom Voltage (Max) (mA)
tpd @ Nom Voltage (Max) (ns)
IOL (Max) (mA)
Input Type
Output Type
Logic
3-State Output
Schmitt Trigger
Rating
Operating Temperature Range (C)
Package Group
Package Size: mm2:W x L (PKG)
SN74LVC2G74-EP SN74LVC2G74 SN74LVC2G74-Q1
LVC     LVC     LVC    
D-Type Flip-Flop     D-Type Flip-Flop     D-Type Flip-Flop    
FLIP-FLOP     FLIP-FLOP     FLIP-FLOP    
1.65     1.65     1.65    
5.5     5.5     5.5    
1     1     1    
1.8
2.5
3.3
5    
1.8
2.5
3.3
5    
1.8
2.5
3.3
5    
150     150     150    
0.01     0.01     0.01    
7.9
6.1    
13.4
7.1
5.9
4.1    
14.4
8.1
6.9
5.1    
32     32     32    
CMOS/TTL     CMOS/TTL     CMOS/TTL    
CMOS     CMOS     CMOS    
True     True     True    
No     No     No    
No     No     No    
HiRel Enhanced Product     Catalog     Automotive    
-55 to 125     -40 to 125
-40 to 85    
-40 to 125    
VSSOP     DSBGA
SM8
VSSOP    
VSSOP    
8VSSOP: 6 mm2: 3.1 x 2(VSSOP)     See datasheet (DSBGA)
8SM8: 12 mm2: 4 x 2.95(SM8)
8VSSOP: 6 mm2: 3.1 x 2(VSSOP)    
8VSSOP: 6 mm2: 3.1 x 2(VSSOP)    

其它合格版本 SN74LVC2G74-EP

版本 器件型号 定义
目录 SN74LVC2G74 TI 的标准目录产品
汽车电子 SN74LVC2G74-Q1 Q100 适用于追求零缺陷的高可靠性汽车电子应用的器件