The SNx4HC273 devices are positive-edge-triggered D-type flip-flops with a direct active low clear (CLR) input.
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output.
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|VCC (Min) (V)|
|VCC (Max) (V)|
|F @ Nom Voltage (Max) (Mhz)|
|ICC @ Nom Voltage (Max) (mA)|
|tpd @ Nom Voltage (Max) (ns)|
|Output Drive (IOL/IOH) (Max) (mA)|
|Operating Temperature Range (C)|
|Package Size: mm2:W x L (PKG)|
|-55 to 125|
| CDIP |
| See datasheet (CDIP) |
See datasheet (CFP)