主页 逻辑和电压转换 触发器、锁存器和寄存器 JK 触发器
主页
逻辑和电压转换
触发器、锁存器和寄存器
JK 触发器

SN54107

正在供货

具有清零功能的双通道 J-K 触发器

立即订购
数据表

SN54107

正在供货
数据表 立即订购

产品详情

Number of channels 2 Technology family TTL Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type TTL IOL (max) (mA) -0.4 IOH (max) (mA) 16 Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 2 Technology family TTL Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type TTL IOL (max) (mA) -0.4 IOH (max) (mA) 16 Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 14 130.4652 mm² 19.56 x 6.67
  • Package Options Include Plastic “Small Outline" Packages, Ceramic Chip Carriers, and Plastic and Ceramic DIPs
  • Dependable Texas Instruments Quality and Reliability

 
  • Package Options Include Plastic “Small Outline" Packages, Ceramic Chip Carriers, and Plastic and Ceramic DIPs
  • Dependable Texas Instruments Quality and Reliability

 

The '107 contain two independent J-K flip-flops with individual J-K, clock, and direct clear inputs. The '107 is a positive pulse-triggered flip-flop. The J-K input data is loaded into the master while the clock is high and transferred to the slave and the outputs on the high-to-low clock transition. For these devices the J and K inputs must be stable while the clock is high.

The 'LS107A contain two independent negative-edge-triggered flip-flops. The J and K inputs must be stable prior to the high-to-low clock transition for predictable operation. When the clear is low, it overrides the clock and data inputs forcing the Q output low and the Q\ output high.

The SN54107 and the SN54LS107A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74107 and the SN74LS107A are characterized for operation from 0°C to 70°C.

 

The '107 contain two independent J-K flip-flops with individual J-K, clock, and direct clear inputs. The '107 is a positive pulse-triggered flip-flop. The J-K input data is loaded into the master while the clock is high and transferred to the slave and the outputs on the high-to-low clock transition. For these devices the J and K inputs must be stable while the clock is high.

The 'LS107A contain two independent negative-edge-triggered flip-flops. The J and K inputs must be stable prior to the high-to-low clock transition for predictable operation. When the clear is low, it overrides the clock and data inputs forcing the Q output low and the Q\ output high.

The SN54107 and the SN54LS107A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74107 and the SN74LS107A are characterized for operation from 0°C to 70°C.

 
open-in-new 查找其他 JK 触发器
下载 观看带字幕的视频 视频

您可能感兴趣的相似产品

open-in-new 比较替代产品
功能与比较器件相似
全新 SN74LV2T74-EP 正在供货 具有清零、预设和集成式电平转换器的双通道 D 型触发器增强型产品 Voltage range (1.65V to 5.5V), voltage translation capable

技术文档

star =有关此产品的 TI 精选热门文档
未找到结果。请清除搜索并重试。
查看全部 10
类型 标题 下载最新的英语版本 日期
* 数据表 Dual J-K Flip-Flops With Clear 数据表 1988年 3月 1日
应用手册 Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022年 12月 15日
选择指南 Logic Guide (Rev. AB) 2017年 6月 12日
应用手册 Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
选择指南 逻辑器件指南 2014 (Rev. AA) 最新英语版本 (Rev.AB) 2014年 11月 17日
用户指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
应用手册 Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
应用手册 使用逻辑器件进行设计 (Rev. C) 1997年 6月 1日
应用手册 Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
应用手册 Live Insertion 1996年 10月 1日

设计和开发

如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。

封装 引脚 下载
CDIP (J) 14 查看选项
应遵守 TI 评估类商品的标准条款与条件。

订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

支持和培训

视频