DS92LV2412

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5MHz 至 50MHz 24 位 Channel Link II 解串器

产品详情

Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
WQFN (NKB) 60 81 mm² 9 x 9
  • 24-Bit Data, 3–Bit Control, 5 to 50 MHz Clock
  • Application Payloads up to 1.2 Gbps
  • AC Coupled Interconnects: STP up to 10 m or
    Coax 20+m
  • 1.8 V or 3.3 V Compatible LVCMOS I/O Interface
  • Integrated Terminations on Ser and Des
  • AT-SPEED BIST Mode and Reporting Pin
  • Configurable by Pins or I2C Compatible Serial
    Control Bus
  • Power Down Mode Minimizes Power Dissipation
  • >8 kV HBM ESD Rating
  • SERIALIZER — DS92LV2411
    • Supports Spread Spectrum Clocking (SSC) on
      Inputs
    • Data Scrambler for Reduced EMI
    • DC-Balance Encoder for AC Coupling
    • Selectable Output VOD and Adjustable
      De-emphasis
  • DESERIALIZER — DS92LV2412
    • Random Data Lock; no Reference Clock
      Required
    • Adjustable Input Receiver Equalization
    • LOCK (Real Time Link Status) Reporting Pin
    • Selectable Spread Spectrum Clock Generation
      (SSCG) and Output Slew Rate Control (OS) to
      Reduce EMI
  • 24-Bit Data, 3–Bit Control, 5 to 50 MHz Clock
  • Application Payloads up to 1.2 Gbps
  • AC Coupled Interconnects: STP up to 10 m or
    Coax 20+m
  • 1.8 V or 3.3 V Compatible LVCMOS I/O Interface
  • Integrated Terminations on Ser and Des
  • AT-SPEED BIST Mode and Reporting Pin
  • Configurable by Pins or I2C Compatible Serial
    Control Bus
  • Power Down Mode Minimizes Power Dissipation
  • >8 kV HBM ESD Rating
  • SERIALIZER — DS92LV2411
    • Supports Spread Spectrum Clocking (SSC) on
      Inputs
    • Data Scrambler for Reduced EMI
    • DC-Balance Encoder for AC Coupling
    • Selectable Output VOD and Adjustable
      De-emphasis
  • DESERIALIZER — DS92LV2412
    • Random Data Lock; no Reference Clock
      Required
    • Adjustable Input Receiver Equalization
    • LOCK (Real Time Link Status) Reporting Pin
    • Selectable Spread Spectrum Clock Generation
      (SSCG) and Output Slew Rate Control (OS) to
      Reduce EMI

The DS92LV2411 (Serializer) and DS92LV2412 (Deserializer) chipset translates a parallel 24–bit LVCMOS data interface into a single high-speed CML serial interface with embedded clock information. This single serial stream eliminates skew issues between clock and data, reduces connector size and interconnect cost for transferring a 24-bit, or less, bus over FR-4 printed circuit board backplanes, differential or coax cables.

In addition to the 24-bit data bus interface, the DS92LV2411/12 also features a 3-bit control bus for slow speed signals. This allows implementing video and display applications with up to 24–bits per pixel (RGB888).

Programmable transmit de-emphasis, receive equalization, on-chip scrambling and DC balancing enables long distance transmission over lossy cables and backplanes. The DS92LV2412 automatically locks to incoming data without an external reference clock or special sync patterns, providing easy “plug-and-go” or “hot plug” operation. EMI is minimized by the use of low voltage differential signaling, receiver drive strength control, and spread spectrum clocking capability.

The DS92LV2411/12 chipset is programmable though an I2C interface as well as through Pins. A built-in AT-SPEED BIST feature validates link integrity and may be used for system diagnostics.

The DS92LV2411 is offered in a 48-Pin WQFN and the DS92LV2412 is offered in a 60-Pin WQFN package. Both devices operate over the full industrial temperature range of –40°C to +85°C.

The DS92LV2411 (Serializer) and DS92LV2412 (Deserializer) chipset translates a parallel 24–bit LVCMOS data interface into a single high-speed CML serial interface with embedded clock information. This single serial stream eliminates skew issues between clock and data, reduces connector size and interconnect cost for transferring a 24-bit, or less, bus over FR-4 printed circuit board backplanes, differential or coax cables.

In addition to the 24-bit data bus interface, the DS92LV2411/12 also features a 3-bit control bus for slow speed signals. This allows implementing video and display applications with up to 24–bits per pixel (RGB888).

Programmable transmit de-emphasis, receive equalization, on-chip scrambling and DC balancing enables long distance transmission over lossy cables and backplanes. The DS92LV2412 automatically locks to incoming data without an external reference clock or special sync patterns, providing easy “plug-and-go” or “hot plug” operation. EMI is minimized by the use of low voltage differential signaling, receiver drive strength control, and spread spectrum clocking capability.

The DS92LV2411/12 chipset is programmable though an I2C interface as well as through Pins. A built-in AT-SPEED BIST feature validates link integrity and may be used for system diagnostics.

The DS92LV2411 is offered in a 48-Pin WQFN and the DS92LV2412 is offered in a 60-Pin WQFN package. Both devices operate over the full industrial temperature range of –40°C to +85°C.

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类型 标题 下载最新的英语版本 日期
* 数据表 DS92LV241x 5 to 50 MHz 24-Bit Channel Link II Serializer And Deserializer 数据表 (Rev. E) PDF | HTML 2015年 2月 9日
应用手册 DS15BA101 & DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES (Rev. E) 2013年 4月 29日
用户指南 LV24EVK01 Channel Link II Ser/Des Evaluation Kit User Guide 2012年 1月 25日
设计指南 Channel Link II Design Guide 2011年 1月 21日
应用手册 App Note 1909 DS15BA101 & DS15EA101 Enable Long Reach Apps for Embed Clk SERDES 2009年 3月 2日

设计和开发

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仿真模型

DS92LV2412 IBIS Model

SNLM125.ZIP (146 KB) - IBIS Model
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用户指南: PDF
英语版 (Rev.A): PDF
封装 引脚 下载
WQFN (NKB) 60 查看选项

订购和质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息:
  • 制造厂地点
  • 封装厂地点

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