DS92LV16

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16 位总线 LVDS 串行器/解串器 - 25-80MHz

产品详情

Function SerDes Protocols Channel-Link I Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (MBits) 2560 Input signal BLVDS, LVDS, LVTTL Output signal BLVDS, LVDS, LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
Function SerDes Protocols Channel-Link I Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (MBits) 2560 Input signal BLVDS, LVDS, LVTTL Output signal BLVDS, LVDS, LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
LQFP (PN) 80 196 mm² 14 x 14
  • 25–80 MHz 16:1/1:16 Serializer/Deserializer (2.56Gbps Full Duplex Throughput)
  • Independent Transmitter and Receiver Operation With Separate Clock, Enable, Power Down Pins
  • Hot Plug Protection (Power Up High Impedance) and Synchronization (Receiver Locks To Random Data)
  • Wide +/−5% Reference Clock Frequency Tolerance for Easy System Design Using Locally-Generated Clocks
  • Line and Local Loopback Modes
  • Robust BLVDS Serial Transmission Across Backplanes and Cables for Low EMI
  • No External Coding Required
  • Internal PLL, No External PLL Components Required
  • Single +3.3V Power Supply
  • Low Power: 104mA (typ) Transmitter, 119mA (typ) Receiver at 80MHz
  • ±100mV Receiver Input Threshold
  • Loss of Lock Detection and Reporting Pin
  • Industrial −40 to +85°C Temperature Range
  • >2.5kV HBM ESD
  • Compact, Standard 80-Pin LQFP Package

All trademarks are the property of their respective owners.

  • 25–80 MHz 16:1/1:16 Serializer/Deserializer (2.56Gbps Full Duplex Throughput)
  • Independent Transmitter and Receiver Operation With Separate Clock, Enable, Power Down Pins
  • Hot Plug Protection (Power Up High Impedance) and Synchronization (Receiver Locks To Random Data)
  • Wide +/−5% Reference Clock Frequency Tolerance for Easy System Design Using Locally-Generated Clocks
  • Line and Local Loopback Modes
  • Robust BLVDS Serial Transmission Across Backplanes and Cables for Low EMI
  • No External Coding Required
  • Internal PLL, No External PLL Components Required
  • Single +3.3V Power Supply
  • Low Power: 104mA (typ) Transmitter, 119mA (typ) Receiver at 80MHz
  • ±100mV Receiver Input Threshold
  • Loss of Lock Detection and Reporting Pin
  • Industrial −40 to +85°C Temperature Range
  • >2.5kV HBM ESD
  • Compact, Standard 80-Pin LQFP Package

All trademarks are the property of their respective owners.

The DS92LV16 Serializer/Deserializer (SERDES) pair transparently translates a 16–bit parallel bus into a BLVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 16-bit, or less bus over PCB traces and cables by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

This SERDES pair includes built-in system and device test capability. The line loopback and local loopback features provide the following functionality: the local loopback enables the user to check the integrity of the transceiver from the local parallel-bus side and the system can check the integrity of the data transmission line by enabling the line loopback.

The DS92LV16 incorporates BLVDS signaling on the high-speed I/O. BLVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. The equal and opposite currents through the differential data path control EMI by coupling the resulting fringing fields together.

The DS92LV16 Serializer/Deserializer (SERDES) pair transparently translates a 16–bit parallel bus into a BLVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 16-bit, or less bus over PCB traces and cables by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

This SERDES pair includes built-in system and device test capability. The line loopback and local loopback features provide the following functionality: the local loopback enables the user to check the integrity of the transceiver from the local parallel-bus side and the system can check the integrity of the data transmission line by enabling the line loopback.

The DS92LV16 incorporates BLVDS signaling on the high-speed I/O. BLVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. The equal and opposite currents through the differential data path control EMI by coupling the resulting fringing fields together.

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类型 标题 下载最新的英语版本 日期
* 数据表 DS92LV16 16-Bit Bus LVDS Serializer/Deserializer - 25 - 80 MHz 数据表 (Rev. H) 2013年 4月 16日
应用手册 DS15BA101 & DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES (Rev. E) 2013年 4月 29日
应用手册 DS92LV16 Power Up Reset (Rev. B) 2013年 4月 26日
应用手册 External Serial Interface Reduces Simultaneous Switching Output Noise in FPGAs (Rev. A) 2013年 4月 26日
应用手册 How to Validate BLVDS SER/DES Signal Integrity Using an Eye Mask (Rev. A) 2013年 4月 26日
应用手册 App Note 1909 DS15BA101 & DS15EA101 Enable Long Reach Apps for Embed Clk SERDES 2009年 3月 2日
设计指南 DS92LV16 16-bit SerDes Design Guide 2007年 3月 29日
白皮书 Easy-to-Use LVDS Serdes for the Serdes Neophyte 2001年 9月 1日

设计和开发

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仿真模型

DS92LV16 IBIS Model

SNLM027.ZIP (18 KB) - IBIS Model
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用户指南: PDF
英语版 (Rev.A): PDF
封装 引脚 下载
LQFP (PN) 80 查看选项

订购和质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息:
  • 制造厂地点
  • 封装厂地点

支持和培训

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