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数据转换器
数模转换器 (DAC)
高速 DAC (> 10MSPS)

DAC5687-EP

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双通道 16 位 500MSPS、1x-8x 内插数模转换器（增强型产品）

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DAC5687-EP

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产品详情

Resolution (Bits) 16 Number of DAC channels 2 Interface type Parallel CMOS Sample/update rate (Msps) 500 Features High Performance Rating HiRel Enhanced Product Interpolation 1x, 2x, 4x, 8x Power consumption (typ) (mW) 1410 SFDR (dB) 78 Architecture Current Sink Operating temperature range (°C) -55 to 125 Reference type Int
Resolution (Bits) 16 Number of DAC channels 2 Interface type Parallel CMOS Sample/update rate (Msps) 500 Features High Performance Rating HiRel Enhanced Product Interpolation 1x, 2x, 4x, 8x Power consumption (typ) (mW) 1410 SFDR (dB) 78 Architecture Current Sink Operating temperature range (°C) -55 to 125 Reference type Int
HTQFP (PZP) 100 256 mm² 16 x 16
  • Controlled Baseline
    • One Assembly
    • One Test Site
    • One Fabrication Site
  • Extended Temperature Performance of –55°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product–Change Notification
  • Qualification Pedigree(1)
  • 500 MSPS
  • Selectable 2×–8× Interpolation
  • On–Chip PLL/VCO Clock Multiplier
  • Full IQ Compensation Including Offset, Gain, and Phase
  • Flexible Input Options
    • FIFO With Latch on External or Internal Clock
    • Even/Odd Multiplexed Input
    • Single–Port Demultiplexed Input
  • Complex Mixer With 32–Bit Numerically Controlled Oscillator (NCO)
  • Fixed–Frequency Mixer With Fs/4 and Fs/2
  • 1.8–V or 3.3–V I/O Voltage
  • On–Chip 1.2–V Reference
  • Differential Scalable Output: 2 mA to 20 mA
  • Pin Compatible to DAC5686
  • High Performance
    • 81–dBc Adjacent Channel Leakage Ratio (ACLR) WCDMA TM1 at 30.72 MHz
    • 72–dBc ACLR WCDMA TM1 at 153.6 MHz
  • Package: 100–Pin HTQFP
  • APPLICATIONS
    • Cellular Base Transceiver Station Transmit Channel
      • CDMA: W–CDMA, CDMA2000, TD–SCDMA
      • TDMA: GSM, IS–136, EDGE/UWC–136
      • OFDM: 802.16
    • Cable Modem Termination System

(1)Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
  • Controlled Baseline
    • One Assembly
    • One Test Site
    • One Fabrication Site
  • Extended Temperature Performance of –55°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product–Change Notification
  • Qualification Pedigree(1)
  • 500 MSPS
  • Selectable 2×–8× Interpolation
  • On–Chip PLL/VCO Clock Multiplier
  • Full IQ Compensation Including Offset, Gain, and Phase
  • Flexible Input Options
    • FIFO With Latch on External or Internal Clock
    • Even/Odd Multiplexed Input
    • Single–Port Demultiplexed Input
  • Complex Mixer With 32–Bit Numerically Controlled Oscillator (NCO)
  • Fixed–Frequency Mixer With Fs/4 and Fs/2
  • 1.8–V or 3.3–V I/O Voltage
  • On–Chip 1.2–V Reference
  • Differential Scalable Output: 2 mA to 20 mA
  • Pin Compatible to DAC5686
  • High Performance
    • 81–dBc Adjacent Channel Leakage Ratio (ACLR) WCDMA TM1 at 30.72 MHz
    • 72–dBc ACLR WCDMA TM1 at 153.6 MHz
  • Package: 100–Pin HTQFP
  • APPLICATIONS
    • Cellular Base Transceiver Station Transmit Channel
      • CDMA: W–CDMA, CDMA2000, TD–SCDMA
      • TDMA: GSM, IS–136, EDGE/UWC–136
      • OFDM: 802.16
    • Cable Modem Termination System

(1)Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

The DAC5687 is a dual–channel 16–bit high–speed digital–to–analog converter (DAC) with integrated 2×, 4×, and 8× interpolation filters, a complex numerically controlled oscillator (NCO), on–board clock multiplier, IQ compensation, and on–chip voltage reference. The DAC5687 is pin compatible to the DAC5686, requiring only changes in register settings for most applications, and offers additional features and superior linearity, noise, crosstalk, and phase-locked loop (PLL) noise performance.

The DAC5687 has six signal processing blocks: two interpolate by two digital filters, a fine–frequency mixer with 32–bit NCO, a quadrature modulation compensation block, another interpolate by two digital filter, and a coarse–frequency mixer with Fs/2 or Fs/4. The different modes of operation enable or bypass the signal processing blocks.

The coarse and fine mixers can be combined to span a wider range of frequencies with fine resolution. The DAC5687 allows both complex or real output. Combining the frequency upconversion and complex output produces a Hilbert Transform pair that is output from the two DACs. An external RF quadrature modulator then performs the final single sideband upconversion.

The IQ compensation feature allows optimization of phase, gain, and offset to maximize sideband rejection and minimize LO feedthrough for an analog quadrature modulator.

The DAC5687 includes several input options: single–port interleaved data, even and odd multiplexing at half rate, and an input FIFO with either external or internal clock to ease the input timing ambiguity when the DAC5687 is clocked at the DAC output sample rate.

The DAC5687 is a dual–channel 16–bit high–speed digital–to–analog converter (DAC) with integrated 2×, 4×, and 8× interpolation filters, a complex numerically controlled oscillator (NCO), on–board clock multiplier, IQ compensation, and on–chip voltage reference. The DAC5687 is pin compatible to the DAC5686, requiring only changes in register settings for most applications, and offers additional features and superior linearity, noise, crosstalk, and phase-locked loop (PLL) noise performance.

The DAC5687 has six signal processing blocks: two interpolate by two digital filters, a fine–frequency mixer with 32–bit NCO, a quadrature modulation compensation block, another interpolate by two digital filter, and a coarse–frequency mixer with Fs/2 or Fs/4. The different modes of operation enable or bypass the signal processing blocks.

The coarse and fine mixers can be combined to span a wider range of frequencies with fine resolution. The DAC5687 allows both complex or real output. Combining the frequency upconversion and complex output produces a Hilbert Transform pair that is output from the two DACs. An external RF quadrature modulator then performs the final single sideband upconversion.

The IQ compensation feature allows optimization of phase, gain, and offset to maximize sideband rejection and minimize LO feedthrough for an analog quadrature modulator.

The DAC5687 includes several input options: single–port interleaved data, even and odd multiplexing at half rate, and an input FIFO with either external or internal clock to ease the input timing ambiguity when the DAC5687 is clocked at the DAC output sample rate.
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技术文档

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类型 标题 下载最新的英语版本 日期
* 数据表 16-Bit 500 MSPS 2x-8x Interpolating Dual-Channel DAC 数据表 2006年 6月 1日
* VID DAC5687-EP VID V6206650 2016年 6月 21日
* 辐射与可靠性报告 DAC5687MPZPEP Reliability Report 2011年 10月 24日
应用手册 High Speed, Digital-to-Analog Converters Basics (Rev. A) 2012年 10月 23日
应用手册 所选封装材料的热学和电学性质 2008年 10月 16日
应用手册 高速数据转换 英语版 2008年 10月 16日
应用手册 CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters 2008年 6月 8日
应用手册 Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 2008年 6月 2日

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包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
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  • 封装厂地点

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