产品详情

Resolution (Bits) 14 Number of DAC channels 2 Interface type Parallel CMOS Sample/update rate (Msps) 275 Features Low Power Rating Catalog Interpolation 1x Power consumption (typ) (mW) 330 SFDR (dB) 84 Architecture Current Source Operating temperature range (°C) -40 to 85 Reference type Int
Resolution (Bits) 14 Number of DAC channels 2 Interface type Parallel CMOS Sample/update rate (Msps) 275 Features Low Power Rating Catalog Interpolation 1x Power consumption (typ) (mW) 330 SFDR (dB) 84 Architecture Current Source Operating temperature range (°C) -40 to 85 Reference type Int
TQFP (PFB) 48 81 mm² 9 x 9
  • 14-Bit Dual Transmit Digital-to-Analog Converter (DAC)
  • 275 MSPS Update Rate
  • Single-Supply: 3 V to 3.6 V
  • High Spurious-Free Dynamic Range (SFDR): 84 dBc at 5 MHz
  • High Third-Order Two-Tone Intermodulation (IMD3): 79 dBc at 15.1 MHz and 16.1 MHz
  • WCDMA Adjacent Channel Leakage Ratio (ACLR): 78 dB at Baseband
  • WCDMA ACLR: 73 dB at 30.72 MHz
  • Independent or Single Resistor Gain Control
  • Dual or Interleaved Data
  • On-Chip 1.2-V Reference
  • Low Power: 330 mW
  • Power-Down Mode: 9 mW
  • Package: 48-Pin Thin-Quad Flat Pack (TQFP)
  • 14-Bit Dual Transmit Digital-to-Analog Converter (DAC)
  • 275 MSPS Update Rate
  • Single-Supply: 3 V to 3.6 V
  • High Spurious-Free Dynamic Range (SFDR): 84 dBc at 5 MHz
  • High Third-Order Two-Tone Intermodulation (IMD3): 79 dBc at 15.1 MHz and 16.1 MHz
  • WCDMA Adjacent Channel Leakage Ratio (ACLR): 78 dB at Baseband
  • WCDMA ACLR: 73 dB at 30.72 MHz
  • Independent or Single Resistor Gain Control
  • Dual or Interleaved Data
  • On-Chip 1.2-V Reference
  • Low Power: 330 mW
  • Power-Down Mode: 9 mW
  • Package: 48-Pin Thin-Quad Flat Pack (TQFP)

The DAC5672 device is a monolithic, dual-channel, 14-bit, high-speed DAC with on-chip voltage reference.

Operating with update rates of up to 275 MSPS, the DAC5672 offers exceptional dynamic performance, tight-gain, and offset matching characteristics that make the device well-suited in I/Q baseband or direct IF communication applications.

Each DAC has a high-impedance, differential-current output suitable for single-ended or differential analog-output configurations. External resistors allow scaling the full-scale output current for each DAC separately or together, typically between 2 mA and 20 mA. An accurate on-chip voltage reference is temperature-compensated and delivers a stable 1.2-V reference voltage. Optionally, an external reference may be used.

The DAC5672 has two, 14-bit, parallel input ports with separate clocks and data latches. For flexibility, the DAC5672 supports multiplexed data for each DAC on one port when operating in interleaved mode.

The DAC5672 is specifically designed for a differential transformer-coupled output with a 50-Ω doubly-terminated load. For a 20-mA full-scale output current, a 4:1 impedance ratio (resulting in an output power of 4 dBm) and 1:1 impedance ratio transformer (–2 dBm output power) are supported.

The DAC5672 is available in a 48-pin TQFP package. Pin compatibility between family members provides 12-bit (DAC5662) and 14-bit (DAC5672) resolutions. Furthermore, the DAC5672 is pin compatible to the DAC2904 and AD9767 dual DACs. The device is characterized for operation over the industrial temperature range from –40°C to 85°C.

The DAC5672 device is a monolithic, dual-channel, 14-bit, high-speed DAC with on-chip voltage reference.

Operating with update rates of up to 275 MSPS, the DAC5672 offers exceptional dynamic performance, tight-gain, and offset matching characteristics that make the device well-suited in I/Q baseband or direct IF communication applications.

Each DAC has a high-impedance, differential-current output suitable for single-ended or differential analog-output configurations. External resistors allow scaling the full-scale output current for each DAC separately or together, typically between 2 mA and 20 mA. An accurate on-chip voltage reference is temperature-compensated and delivers a stable 1.2-V reference voltage. Optionally, an external reference may be used.

The DAC5672 has two, 14-bit, parallel input ports with separate clocks and data latches. For flexibility, the DAC5672 supports multiplexed data for each DAC on one port when operating in interleaved mode.

The DAC5672 is specifically designed for a differential transformer-coupled output with a 50-Ω doubly-terminated load. For a 20-mA full-scale output current, a 4:1 impedance ratio (resulting in an output power of 4 dBm) and 1:1 impedance ratio transformer (–2 dBm output power) are supported.

The DAC5672 is available in a 48-pin TQFP package. Pin compatibility between family members provides 12-bit (DAC5662) and 14-bit (DAC5672) resolutions. Furthermore, the DAC5672 is pin compatible to the DAC2904 and AD9767 dual DACs. The device is characterized for operation over the industrial temperature range from –40°C to 85°C.

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类型 标题 下载最新的英语版本 日期
* 数据表 Dual 14 Bit 275 MSPS DAC 数据表 (Rev. D) 2017年 8月 4日
用户指南 TSW6011EVM Quick Start Guide (Rev. D) 2016年 8月 17日
应用手册 Wideband Complementary Current Output DAC Single-Ended Interface (Rev. A) 2015年 5月 8日
设计指南 Direct Down-Conversion System With I/Q Correction (TIDA-00078 CerTIfied Design) 2013年 7月 23日
应用手册 High Speed, Digital-to-Analog Converters Basics (Rev. A) 2012年 10月 23日
应用手册 Passive Terminations for Current Output DACs 2008年 11月 10日
应用手册 所选封装材料的热学和电学性质 2008年 10月 16日
应用手册 高速数据转换 英语版 2008年 10月 16日
应用手册 CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters 2008年 6月 8日
应用手册 Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 2008年 6月 2日
EVM 用户指南 DAC5672/62/52 14- and 12-Bit Dual Channel DAC EVM (Rev. B) 2006年 3月 24日

设计和开发

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评估板

DAC5672EVM — DAC5672 评估模块

This tool is designed to enable DAC5672 evaluation under various signals, reference and supply conditions.

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仿真模型

DAC5672 IBIS Model (Rev. A)

SLWC060A.ZIP (6 KB) - IBIS Model
计算工具

MATCHGAIN-CALC — 宽带辅助电流输出 DAC 转 SE 接口:增益和合规电压摆幅的改进匹配

NOTE: Calculator software is available when downloading the application note.
  • Click on "abstract" to view abstract of document.
  • Open the ZIP file to extract the calculator tool.
  • Open the PDF file to view the application note.

High-speed digital-to-analog converters (DACs) most often use a (...)

模拟工具

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参考设计

TIDA-00078 — 具有 I/Q 校正的直接降压转换系统

TSW6011EVM 的现场可编程门阵列 (FPGA) 中实施的 I/Q 校正块可帮助用户在无线系统中采用直接降压转换接收器架构。I/Q 校正块包含一个单头盲算法,该算法可以校正零中频接收器系统中与频率无关的 I/Q 不平衡。除了 I/Q 校正块,FPGA 还包括一个数字增益块、一个数字功率测量块、两个内插块、一个 I/Q 偏移校正块和一个正交混频块。
设计指南: PDF
原理图: PDF
封装 引脚 下载
TQFP (PFB) 48 查看选项

订购和质量

包含信息:
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  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息:
  • 制造厂地点
  • 封装厂地点

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