产品详情

Function Clock generator Number of outputs 4 Output frequency (max) (MHz) 683.264 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type LVCMOS, XTAL Output type LVPECL Operating temperature range (°C) -40 to 85 Features 3.3-V VCC/VDD, Pin programmable Rating Catalog
Function Clock generator Number of outputs 4 Output frequency (max) (MHz) 683.264 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type LVCMOS, XTAL Output type LVPECL Operating temperature range (°C) -40 to 85 Features 3.3-V VCC/VDD, Pin programmable Rating Catalog
VQFN (RHB) 32 25 mm² 5 x 5
  • One Crystal/LVCMOS Reference Input
    Including 24.8832 MHz, 25 MHz, and 26.5625 MHz
  • Input Frequency Range: 21.875 MHz to
    28.47 MHz
  • On-Chip VCO Operates in Frequency Range of

    1.75 GHz to 2.05 GHz
  • 4x Output Available:
    • Pin-Selectable Between LVPECL, LVDS, or
      2-LVCMOS; Operates at 3.3 V
  • LVCMOS Bypass Output Available
  • Output Frequency Selectable by /1, /2, /3, /4, /6,
    /8 from a Single Output Divider
  • Supports Common LVPECL/LVDS Output
    Frequencies:
    • 62.5 MHz, 74.25 MHz, 75 MHz, 77.76 MHz,
      100 MHz, 106.25 MHz, 125 MHz, 150 MHz,
      155.52 MHz, 156.25 MHz, 159.375 MHz,
      187.5 MHz, 200 MHz, 212.5 MHz, 250 MHz,
      311.04 MHz, 312.5 MHz, 622.08 MHz,
      625 MHz
  • Supports Common LVCMOS Output Frequencies:
    • 62.5 MHz, 74.25 MHz, 75 MHz, 77.76 MHz,
      100 MHz, 106.25 MHz, 125 MHz, 150 MHz,
      155.52 MHz, 156.25 MHz, 159.375 MHz,
      187.5 MHz, 200 MHz, 212.5 MHz, 250 MHz
  • Output Frequency Range: 43.75 MHz to
    683.264 MHz
  • Internal PLL Loop Bandwidth: 400 kHz
  • High-Performance PLL Core:
    • Phase Noise typically at –146 dBc/Hz at
      5-MHz Offset for 625-MHz LVPECL Output
    • Random Jitter typically at 0.509 ps, RMS
      (10 kHz to 20 MHz) for 625-MHz LVPECL Output
  • Output Duty Cycle Corrected to 50% (± 5%)
  • Low Output Skew of 30 ps on LVPECL Outputs
  • Divider Programming Using Control Pins:
    • Two Pins for Prescaler/Feedback Divider
    • Three Pins for Output Divider
    • Two Pins for Output Select
  • Chip Enable Control Pin Available
  • 3.3-V Core and I/O Power Supply
  • Industrial Temperature Range: –40°C to 85°C
  • 5-mm × 5-mm, 32-pin, VQFN (RHB) Package
  • ESD Protection Exceeds 2 kV (HBM)
  • One Crystal/LVCMOS Reference Input
    Including 24.8832 MHz, 25 MHz, and 26.5625 MHz
  • Input Frequency Range: 21.875 MHz to
    28.47 MHz
  • On-Chip VCO Operates in Frequency Range of

    1.75 GHz to 2.05 GHz
  • 4x Output Available:
    • Pin-Selectable Between LVPECL, LVDS, or
      2-LVCMOS; Operates at 3.3 V
  • LVCMOS Bypass Output Available
  • Output Frequency Selectable by /1, /2, /3, /4, /6,
    /8 from a Single Output Divider
  • Supports Common LVPECL/LVDS Output
    Frequencies:
    • 62.5 MHz, 74.25 MHz, 75 MHz, 77.76 MHz,
      100 MHz, 106.25 MHz, 125 MHz, 150 MHz,
      155.52 MHz, 156.25 MHz, 159.375 MHz,
      187.5 MHz, 200 MHz, 212.5 MHz, 250 MHz,
      311.04 MHz, 312.5 MHz, 622.08 MHz,
      625 MHz
  • Supports Common LVCMOS Output Frequencies:
    • 62.5 MHz, 74.25 MHz, 75 MHz, 77.76 MHz,
      100 MHz, 106.25 MHz, 125 MHz, 150 MHz,
      155.52 MHz, 156.25 MHz, 159.375 MHz,
      187.5 MHz, 200 MHz, 212.5 MHz, 250 MHz
  • Output Frequency Range: 43.75 MHz to
    683.264 MHz
  • Internal PLL Loop Bandwidth: 400 kHz
  • High-Performance PLL Core:
    • Phase Noise typically at –146 dBc/Hz at
      5-MHz Offset for 625-MHz LVPECL Output
    • Random Jitter typically at 0.509 ps, RMS
      (10 kHz to 20 MHz) for 625-MHz LVPECL Output
  • Output Duty Cycle Corrected to 50% (± 5%)
  • Low Output Skew of 30 ps on LVPECL Outputs
  • Divider Programming Using Control Pins:
    • Two Pins for Prescaler/Feedback Divider
    • Three Pins for Output Divider
    • Two Pins for Output Select
  • Chip Enable Control Pin Available
  • 3.3-V Core and I/O Power Supply
  • Industrial Temperature Range: –40°C to 85°C
  • 5-mm × 5-mm, 32-pin, VQFN (RHB) Package
  • ESD Protection Exceeds 2 kV (HBM)

The CDCM61004 is a highly versatile, low-jitter frequency synthesizer capable of generating four low-jitter clock outputs, selectable between low-voltage positive emitter coupled logic (LVPECL), low-voltage differential signaling (LVDS), or low-voltage complementary metal oxide semiconductor (LVCMOS) outputs, from a low-frequency crystal of LVCMOS input for a variety of wireline and data communication applications. The CDCM61004 features an onboard PLL that can be easily configured solely through control pins. The overall output random jitter performance is less than 1 ps, RMS (from 10 kHz to 20 MHz), making this device a perfect choice for use in demanding applications such as SONET, Ethernet, Fibre Channel, and SAN. The CDCM61004 is available in a small, 32-pin, 5-mm × 5-mm VQFN package.

The CDCM61004 is a high-performance, low-phase noise, fully-integrated voltage-controlled oscillator (VCO) clock synthesizer with four universal output buffers that can be configured to be LVPECL, LVDS, or LVCMOS compatible. Each universal output can also be converted to two LVCMOS outputs. Additionally, an LVCMOS bypass output clock is available in an output configuration which can help with crystal loading to achieve an exact desired input frequency. It has one fully-integrated, low-noise, LC-based VCO that operates in the
1.75 GHz to 2.05 GHz range.

The phase-locked loop (PLL) synchronizes the VCO with respect to the input, which can either be a low-frequency crystal. The output share an output divider sourced from the VCO core. All device settings are managed through a control pin structure, which has two pins that control the prescaler and feedback divider, three pins that control the output divider, two pins that control the output type, and one pin that controls the output enable. Any time the PLL settings (including the input frequency, prescaler divider, or feedback divider) are altered, a reset must be issued through the Reset control pin (active low for device reset). The reset initiates a PLL recalibration process to ensure PLL lock. When the device is in reset, the outputs and dividers are turned off.

The output frequency (fOUT) is proportional to the frequency of the input clock (fIN). The feedback divider, output divider, and VCO frequency set fOUT with respect to fIN.

The output divider can be chosen from 1, 2, 3, 4, 6, or 8 through the use of control pins. Feedback divider and prescaler divider combinations can be chosen from 25 and 3, 24 and 3, 20 and 4, or 15 and 5, respectively, also through the use of control pins. CDCM61004 Block Diagram shows a high-level diagram of the CDCM61004.

The device operates in a 3.3-V supply environment and is characterized for operation from –40°C to 85°C.

The CDCM61004 is a highly versatile, low-jitter frequency synthesizer capable of generating four low-jitter clock outputs, selectable between low-voltage positive emitter coupled logic (LVPECL), low-voltage differential signaling (LVDS), or low-voltage complementary metal oxide semiconductor (LVCMOS) outputs, from a low-frequency crystal of LVCMOS input for a variety of wireline and data communication applications. The CDCM61004 features an onboard PLL that can be easily configured solely through control pins. The overall output random jitter performance is less than 1 ps, RMS (from 10 kHz to 20 MHz), making this device a perfect choice for use in demanding applications such as SONET, Ethernet, Fibre Channel, and SAN. The CDCM61004 is available in a small, 32-pin, 5-mm × 5-mm VQFN package.

The CDCM61004 is a high-performance, low-phase noise, fully-integrated voltage-controlled oscillator (VCO) clock synthesizer with four universal output buffers that can be configured to be LVPECL, LVDS, or LVCMOS compatible. Each universal output can also be converted to two LVCMOS outputs. Additionally, an LVCMOS bypass output clock is available in an output configuration which can help with crystal loading to achieve an exact desired input frequency. It has one fully-integrated, low-noise, LC-based VCO that operates in the
1.75 GHz to 2.05 GHz range.

The phase-locked loop (PLL) synchronizes the VCO with respect to the input, which can either be a low-frequency crystal. The output share an output divider sourced from the VCO core. All device settings are managed through a control pin structure, which has two pins that control the prescaler and feedback divider, three pins that control the output divider, two pins that control the output type, and one pin that controls the output enable. Any time the PLL settings (including the input frequency, prescaler divider, or feedback divider) are altered, a reset must be issued through the Reset control pin (active low for device reset). The reset initiates a PLL recalibration process to ensure PLL lock. When the device is in reset, the outputs and dividers are turned off.

The output frequency (fOUT) is proportional to the frequency of the input clock (fIN). The feedback divider, output divider, and VCO frequency set fOUT with respect to fIN.

The output divider can be chosen from 1, 2, 3, 4, 6, or 8 through the use of control pins. Feedback divider and prescaler divider combinations can be chosen from 25 and 3, 24 and 3, 20 and 4, or 15 and 5, respectively, also through the use of control pins. CDCM61004 Block Diagram shows a high-level diagram of the CDCM61004.

The device operates in a 3.3-V supply environment and is characterized for operation from –40°C to 85°C.

下载 观看带字幕的视频 视频

您可能感兴趣的相似产品

open-in-new 比较替代产品
功能与比较器件相同且具有相同引脚
CDCM61001 正在供货 1:1 超低抖动晶振时钟发生器 The same pin-pin compatible family with different number of outputs
CDCM61002 正在供货 1:2 超低抖动晶振时钟发生器 The same pin-pin compatible family with different number of outputs
功能与比较器件相同但引脚有所不同
CDCM6208 正在供货 2:8 超低功耗、低抖动时钟发生器 CDCM6208 has higher performance comapared to CDCM61004
功能与比较器件相似
CDCE62005 正在供货 具有集成双通道 VCO 的 5/10 路输出时钟发生器/抖动消除器 CDCSM6100x performs a subset function of CDCE62005 with more easy to use feature

技术文档

star =有关此产品的 TI 精选热门文档
未找到结果。请清除搜索并重试。
查看全部 6
类型 标题 下载最新的英语版本 日期
* 数据表 CDCM61004 Four Output, Integrated VCO, Low-Jitter Clock Generator 数据表 (Rev. H) PDF | HTML 2016年 1月 13日
用户指南 Low Phase Noise Clock Evaluation Module (Rev. B) 2011年 3月 2日
应用手册 Using LVCMOS Input to the CDCM6100x 2010年 5月 23日
模拟设计期刊 TI Powers Altera's Arria II GX FPGA Development Kit 2009年 9月 29日
应用手册 Ethernet Clock Generation Using the CDCM6100x 2009年 2月 18日
应用手册 Fibre Channel and SAN Clock Generation Using the CDCM6100x 2009年 2月 18日

设计和开发

如需其他信息或资源,请点击以下任一标题进入详情页面查看(如有)。

评估板

CDCM6100XEVM — CDCM61004/CDCM61002/CDCM61001 评估模块

CDCM6100xEVM is the evaluation module for CDCM61004 or CDCM61002 or CDCM61001. CDCM61004/2/1 family is a highly versatile, ultra low-jitter frequency synthesizer family that can generate four/two/one low-jitter clock output pairs, selectable among LVPECL, LVDS, or 2 LVCMOS, from a low-frequency (...)

用户指南: PDF
TI.com 上无现货
仿真模型

CDCM61004 IBIS Model (Rev. B)

SLLM061B.ZIP (64 KB) - IBIS Model
模拟工具

PSPICE-FOR-TI — 适用于 TI 设计和模拟工具的 PSpice®

PSpice® for TI 可提供帮助评估模拟电路功能的设计和仿真环境。此功能齐全的设计和仿真套件使用 Cadence® 的模拟分析引擎。PSpice for TI 可免费使用,包括业内超大的模型库之一,涵盖我们的模拟和电源产品系列以及精选的模拟行为模型。

借助 PSpice for TI 的设计和仿真环境及其内置的模型库,您可对复杂的混合信号设计进行仿真。创建完整的终端设备设计和原型解决方案,然后再进行布局和制造,可缩短产品上市时间并降低开发成本。

在 PSpice for TI 设计和仿真工具中,您可以搜索 TI (...)
封装 引脚 下载
VQFN (RHB) 32 查看选项

订购和质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息:
  • 制造厂地点
  • 封装厂地点

推荐产品可能包含与 TI 此产品相关的参数、评估模块或参考设计。

支持和培训

视频