产品详情

Arm CPU 1 Arm9 Arm (max) (MHz) 300 Coprocessors PRU-ICSS CPU 32-bit Protocols Ethernet Ethernet MAC 1-Port 10/100 Operating system Linux, RTOS Security Device identity, Memory protection Rating Catalog Operating temperature range (°C) -40 to 90
Arm CPU 1 Arm9 Arm (max) (MHz) 300 Coprocessors PRU-ICSS CPU 32-bit Protocols Ethernet Ethernet MAC 1-Port 10/100 Operating system Linux, RTOS Security Device identity, Memory protection Rating Catalog Operating temperature range (°C) -40 to 90
NFBGA (ZCE) 361 169 mm² 13 x 13 NFBGA (ZWT) 361 256 mm² 16 x 16
  • 300-MHzARM926EJ-S RISC MPU
  • ARM926EJ-S Core
    • 32-Bit and 16-Bit (Thumb) Instructions
    • Single-Cycle MAC
    • ARM Jazelle Technology
    • Embedded ICE-RT for Real-Time Debug
  • ARM9 Memory Architecture
    • 16KB of Instruction Cache
    • 16KB of Data Cache
    • 8KB of RAM (Vector Table)
    • 64KB of ROM
  • Enhanced Direct Memory Access Controller 3 (EDMA3):
    • 2 Channel Controllers
    • 3 Transfer Controllers
    • 64 Independent DMA Channels
    • 16 Quick DMA Channels
    • Programmable Transfer Burst Size
  • 128KB of On-Chip Memory
  • 1.8-V or 3.3-V LVCMOS I/Os (Except for USB and DDR2 Interfaces)
  • Two External Memory Interfaces:
    • EMIFA
      • NOR (8- or 16-Bit-Wide Data)
      • NAND (8- or 16-Bit-Wide Data)
      • 16-Bit SDRAM with 128-MB Address Space
    • DDR2/Mobile DDR Memory Controller with one of the following:
      • 16-Bit DDR2 SDRAM with 256-MB Address Space
      • 16-Bit mDDR SDRAM with 256-MB Address Space
  • Three Configurable 16550-Type UART Modules:
    • With Modem Control Signals
    • 16-Byte FIFO
    • 16x or 13x Oversampling Option
  • Two Serial Peripheral Interfaces (SPIs) Each with Multiple Chip Selects
  • One Multimedia Card (MMC)/Secure Digital (SD) Card Interfaces with Secure Data I/O (SDIO) Interfaces
  • One Master and Slave Inter-Integrated Circuit (I2C Bus)
  • USB 2.0 OTG Port with Integrated PHY (USB0)
    • USB 2.0 High- and Full-Speed Client
    • USB 2.0 High-, Full-, and Low-Speed Host
    • End Point 0 (Control)
    • End Points 1, 2, 3, 4 (Control, Bulk, Interrupt or ISOC) RX and TX
  • One Multichannel Audio Serial Port (McASP):
    • Transmit and Receive Clocks
    • Two Clock Zones and 16 Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
    • DIT-Capable
    • FIFO Buffers for Transmit and Receive
  • 10/100 Mbps Ethernet MAC (EMAC):
    • IEEE 802.3 Compliant
    • MII Media-Independent Interface
    • RMII Reduced Media-Independent Interface
    • Management Data I/O (MDIO) Module
  • Real-Time Clock (RTC) with 32-kHz Oscillator and Separate Power Rail
  • Three 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit General-Purpose or Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
  • Packages:
    • 361-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZCE Suffix], 0.65-mm Ball Pitch
    • 361-Ball PBGA [ZWT Suffix], 0.80-mm Ball Pitch
  • Industrial Temperature
  • 300-MHzARM926EJ-S RISC MPU
  • ARM926EJ-S Core
    • 32-Bit and 16-Bit (Thumb) Instructions
    • Single-Cycle MAC
    • ARM Jazelle Technology
    • Embedded ICE-RT for Real-Time Debug
  • ARM9 Memory Architecture
    • 16KB of Instruction Cache
    • 16KB of Data Cache
    • 8KB of RAM (Vector Table)
    • 64KB of ROM
  • Enhanced Direct Memory Access Controller 3 (EDMA3):
    • 2 Channel Controllers
    • 3 Transfer Controllers
    • 64 Independent DMA Channels
    • 16 Quick DMA Channels
    • Programmable Transfer Burst Size
  • 128KB of On-Chip Memory
  • 1.8-V or 3.3-V LVCMOS I/Os (Except for USB and DDR2 Interfaces)
  • Two External Memory Interfaces:
    • EMIFA
      • NOR (8- or 16-Bit-Wide Data)
      • NAND (8- or 16-Bit-Wide Data)
      • 16-Bit SDRAM with 128-MB Address Space
    • DDR2/Mobile DDR Memory Controller with one of the following:
      • 16-Bit DDR2 SDRAM with 256-MB Address Space
      • 16-Bit mDDR SDRAM with 256-MB Address Space
  • Three Configurable 16550-Type UART Modules:
    • With Modem Control Signals
    • 16-Byte FIFO
    • 16x or 13x Oversampling Option
  • Two Serial Peripheral Interfaces (SPIs) Each with Multiple Chip Selects
  • One Multimedia Card (MMC)/Secure Digital (SD) Card Interfaces with Secure Data I/O (SDIO) Interfaces
  • One Master and Slave Inter-Integrated Circuit (I2C Bus)
  • USB 2.0 OTG Port with Integrated PHY (USB0)
    • USB 2.0 High- and Full-Speed Client
    • USB 2.0 High-, Full-, and Low-Speed Host
    • End Point 0 (Control)
    • End Points 1, 2, 3, 4 (Control, Bulk, Interrupt or ISOC) RX and TX
  • One Multichannel Audio Serial Port (McASP):
    • Transmit and Receive Clocks
    • Two Clock Zones and 16 Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
    • DIT-Capable
    • FIFO Buffers for Transmit and Receive
  • 10/100 Mbps Ethernet MAC (EMAC):
    • IEEE 802.3 Compliant
    • MII Media-Independent Interface
    • RMII Reduced Media-Independent Interface
    • Management Data I/O (MDIO) Module
  • Real-Time Clock (RTC) with 32-kHz Oscillator and Separate Power Rail
  • Three 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit General-Purpose or Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
  • Packages:
    • 361-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZCE Suffix], 0.65-mm Ball Pitch
    • 361-Ball PBGA [ZWT Suffix], 0.80-mm Ball Pitch
  • Industrial Temperature

The AM1802 ARM microprocessor is a low-power applications processor based on ARM926EJ-S.

The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core has a coprocessor 15 (CP15), protection module, and data and program memory management units (MMUs) with table look-aside buffers. The ARM core processor has separate 16-KB instruction and 16-KB data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core also has 8KB of RAM (Vector Table) and 64KB of ROM.

The peripheral set includes: a 10/100 Mbps Ethernet media access controller (EMAC) with a management data input/output (MDIO) module; one USB2.0 OTG interface; one inter-integrated circuit (I2C Bus) interface; one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; two serial peripheral interfaces (SPIs) with multiple chip selects; four 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host-port interface (HPI); up to 9 banks of general-purpose input/output (GPIO) pins, with each bank containing 16 pins with programmable interrupt and event generation modes, multiplexed with other peripherals; three UART interfaces (each with RTS and CTS); two external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals; and a higher speed DDR2/Mobile DDR controller.

The EMAC provides an efficient interface between the device and a network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration. The EMAC supports both MII and RMII interfaces.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections in this document and the associated peripheral reference guides.

The device has a complete set of development tools for the ARM processor. These tools include C compilers, and scheduling, and a Windows debugger interface for visibility into source code execution.

The AM1802 ARM microprocessor is a low-power applications processor based on ARM926EJ-S.

The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core has a coprocessor 15 (CP15), protection module, and data and program memory management units (MMUs) with table look-aside buffers. The ARM core processor has separate 16-KB instruction and 16-KB data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core also has 8KB of RAM (Vector Table) and 64KB of ROM.

The peripheral set includes: a 10/100 Mbps Ethernet media access controller (EMAC) with a management data input/output (MDIO) module; one USB2.0 OTG interface; one inter-integrated circuit (I2C Bus) interface; one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; two serial peripheral interfaces (SPIs) with multiple chip selects; four 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host-port interface (HPI); up to 9 banks of general-purpose input/output (GPIO) pins, with each bank containing 16 pins with programmable interrupt and event generation modes, multiplexed with other peripherals; three UART interfaces (each with RTS and CTS); two external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals; and a higher speed DDR2/Mobile DDR controller.

The EMAC provides an efficient interface between the device and a network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration. The EMAC supports both MII and RMII interfaces.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections in this document and the associated peripheral reference guides.

The device has a complete set of development tools for the ARM processor. These tools include C compilers, and scheduling, and a Windows debugger interface for visibility into source code execution.

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类型 标题 下载最新的英语版本 日期
* 数据表 AM1802 ARM Microprocessor 数据表 (Rev. E) PDF | HTML 2014年 3月 21日
* 勘误表 AM1802 ARM Microprocessor Silicon Errata (Revs 2.3, 2.1 and 2.0) (Rev. H) 2014年 9月 17日
用户指南 ARM 优化 C/C++ 编译器 v20.2.0.LTS (Rev. W) PDF | HTML 英语版 (Rev.W) PDF | HTML 2023年 4月 13日
用户指南 ARM 汇编语言工具 v20.2.0.LTS (Rev. Z) PDF | HTML 英语版 (Rev.Z) PDF | HTML 2023年 4月 13日
应用手册 Programming mDDR/DDR2 EMIF on OMAP-L1x/C674x 2019年 12月 20日
用户指南 ARM Assembly Language Tools v19.6.0.STS User's Guide (Rev. X) 2019年 6月 3日
用户指南 ARM Optimizing C/C++ Compiler v19.6.0.STS User's Guide (Rev. U) 2019年 6月 3日
应用手册 Programming PLL Controllers on OMAP-L1x8/C674x/AM18xx 2019年 4月 25日
应用手册 General Hardware Design/BGA PCB Design/BGA 2019年 2月 22日
应用手册 Using the AM18xx Bootloader (Rev. D) PDF | HTML 2019年 1月 22日
用户指南 ARM Assembly Language Tools v18.12.0.LTS User's Guide (Rev. W) 2018年 11月 19日
用户指南 ARM Optimizing C/C++ Compiler v18.12.0.LTS User's Guide (Rev. T) 2018年 11月 19日
用户指南 How-To and Troubleshooting Guide for PRU-ICSS PROFIBUS 2018年 9月 24日
用户指南 ARM Assembly Language Tools v18.1.0.LTS User's Guide (Rev. U) 2018年 1月 16日
用户指南 ARM Optimizing C/C++ Compiler v18.1.0.LTS User's Guide (Rev. R) 2018年 1月 16日
用户指南 ARM Assembly Language Tools v17.9.0.STS User's Guide (Rev. T) 2017年 9月 30日
用户指南 ARM Optimizing C/C++ Compiler v17.9.0.STS User's Guide (Rev. Q) 2017年 9月 30日
用户指南 ARM Assembly Language Tools v17.6.0.STS User's Guide (Rev. S) 2017年 6月 21日
用户指南 ARM Optimizing C/C++ Compiler v17.6.0.STS User's Guide (Rev. P) 2017年 6月 21日
用户指南 AM1802 ARM Microprocessor Technical Reference Manual (Rev. C) 2016年 9月 12日
用户指南 ARM Assembly Language Tools v16.9.0.LTS User's Guide (Rev. P) 2016年 4月 30日
用户指南 ARM Optimizing C/C++ Compiler v16.9.0.LTS User's Guide (Rev. M) 2016年 4月 30日
技术文章 Spring has sprung. A sale has sprung. PDF | HTML 2016年 4月 4日
用户指南 ARM Assembly Language Tools v5.2 User's Guide (Rev. M) 2014年 11月 5日
用户指南 ARM Optimizing C/C++ Compiler v5.2 User's Guide (Rev. J) 2014年 11月 5日
应用手册 AM18xx Pin Multiplexing Utility (Rev. A) 2011年 12月 6日
应用手册 AM18x power consumption summary 2010年 8月 30日

设计和开发

如需其他信息或资源,请点击以下任一标题进入详情页面查看(如有)。

调试探针

TMDSEMU200-U — XDS200 USB 调试探针

XDS200 是用于调试 TI 嵌入式器件的调试探针(仿真器)。与低成本的 XDS110 和高性能的 XDS560v2 相比,XDS200 在低成本和高性能之间实现了平衡;并在单个仓体中支持广泛的标准(IEEE1149.1、IEEE1149.7、SWD)。所有 XDS 调试探针在所有具有嵌入式跟踪缓冲器 (ETB) 的 Arm® 和 DSP 处理器中均支持内核和系统跟踪。对于引脚上的内核跟踪,则需要使用 XDS560v2 PRO TRACE

XDS200 通过 TI 20 引脚连接器(带有适用于 TI 14 引脚、Arm Cortex® 10 引脚和 Arm 20 (...)

TI.com 上无现货
调试探针

TMDSEMU560V2STM-U — XDS560™ 软件 v2 系统跟踪 USB 调试探针

XDS560v2 是 XDS560™ 系列调试探针中性能非常出色的产品,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。请注意,它不支持串行线调试 (SWD)。

所有 XDS 调试探针在所有具有嵌入式跟踪缓冲器 (ETB) 的 ARM 和 DSP 处理器中均支持内核和系统跟踪。对于引脚上的跟踪,需要 XDS560v2 PRO TRACE

XDS560v2 通过 MIPI HSPT 60 引脚连接器(带有多个用于 TI 14 引脚、TI 20 引脚和 ARM 20 引脚的适配器)连接到目标板,并通过 USB2.0 高速 (480Mbps) (...)

TI.com 上无现货
调试探针

TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 系统跟踪 USB 和以太网

XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针(仿真器)的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件,通过捕获相关器件级信息,获得准确的总线性能活动和吞吐量,并对内核和外设进行电源管理。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS (...)

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软件开发套件 (SDK)

LINUXEZSDK-SITARA — 用于 Sitara™ ARM® 处理器的 Linux EZ 软件开发套件 (EZSDK)

Linux EZ 软件开发套件 (EZ SDK) 为 Sitara™ 开发人员提供了提供了轻松设置、开包即用的快捷体验(特定于且突出了 Sitara ARM9® 和 Cortex™ -A8® 微处理器的特性)。使用附带的图形用户界面,即可轻松启用演示、基准和应用。Sitara Linux EZ SDK 还可使开发人员快速开始开发其自己的应用,并将其轻松添加至由开发人员定制的应用程序启动器中。
软件开发套件 (SDK)

PRU-SWPKG 可编程实时单元 (PRU) 软件支持包

The PRU Software Support Package is an add-on package that provides a framework and examples for developing software for the Programmable Real-time Unit sub-system and Industrial Communication Sub-System (PRU-ICSS) in the supported TI processors.  The PRU-ICSS achieves deterministic, real-time (...)

支持的产品和硬件

支持的产品和硬件

产品
基于 Arm 的处理器
AM1802 Sitara 处理器: Arm9,LPDDR,DDR2,以太网 AM1806 Sitara 处理器: Arm9,LPDDR,DDR2,显示 AM1808 Sitara 处理器: Arm9,LPDDR,DDR2,显示,以太网 AM1810 Sitara 处理器: Arm9,LPDDR,DDR2,显示,以太网,PROFIBUS AM4377 Sitara 处理器: Arm Cortex-A9、PRU-ICSS、EtherCAT AM4378 Sitara 处理器: Arm Cortex-A9、PRU-ICSS、3D 图形
软件
PRU-SWPKG 可编程实时单元 (PRU) 软件支持包
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软件开发套件 (SDK)

WINCESDK-AM1XOMAPL1X — 用于 Sitara™ ARM® AM1x /OMAP-L1x 器件的 Windows 嵌入式 CE ™ 软件开发套件 (SDK)

查看 WEP 徽标

 


Microsoft Windows™ 嵌入式 CE* (CE) 6.0 R3 这款操作系统专门针对需要最小存储器(基于组合架构)的嵌入式器件进行了优化。Windows CE 是具有显著特点的内核,它可以在低于 1 兆字节的存储器中运行。它符合实时操作系统的定义,具有确定的中断延迟。专为与 Microsoft 的 Platform Builder 和 Visual Studio 工具配合使用而设计,Windows 嵌入式 CE 6.0 R3 操作系统使开发人员能够使用熟悉的全功能嵌入式设计环境来立即着手开发。通过使用熟悉的标准 Windows 嵌入式 CE 应用编程接口 (...)
驱动程序或库

STARTERWARE-SITARA — 针对 TI Sitara(基于 ARM®)处理器的 StarterWare

StarterWare provides C-based no-OS platform support for TI's ARM9™ and ARM® Cortex™ A8 based devices. StarterWare provides device abstraction layer libraries, peripheral programming examples such as Ethernet, graphics and USB, and board level example applications. StarterWare can be (...)
IDE、配置、编译器或调试器

CCSTUDIO Code Composer Studio 集成式开发环境 (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It comprises a suite of tools used to develop and debug embedded applications.  Code Composer Studio is available for download across Windows®, Linux® and macOS® (...)

支持的产品和硬件

支持的产品和硬件

此设计资源支持这些类别中的大部分产品。

查看产品详情页,验证是否能提供支持。

启动 下载选项
操作系统 (OS)

MG-3P-NUCLEUS-RTOS — Mentor Graphics Nucleus RTOS

Software driven power management is crucial for battery operated or low power budget embedded systems. Embedded developers can now take advantage of the latest power saving features in popular TI devices with the built-in Power Management Framework in the Nucleus RTOS. Developers specify (...)
仿真模型

AM1802 ZCE IBIS Model

SPRM604.ZIP (120 KB) - IBIS Model
仿真模型

AM1802 ZWT BSDL Model

SPRM517.ZIP (8 KB) - BSDL Model
仿真模型

AM1802 ZWT IBIS Model (Rev. A)

SPRM518A.ZIP (121 KB) - IBIS Model
设计工具

PROCESSORS-3P-SEARCH — 基于 Arm® 的 MPU、基于 Arm 的 MCU 和 DSP 第三方搜索工具

TI 已与多家公司合作,提供各种使用 TI 处理器的软件、工具和 SOM,从而加快您的量产速度。下载此搜索工具,快速浏览我们的第三方解决方案,并寻找合适的第三方来满足您的需求。此处所列的软件、工具和模块由独立的第三方生产和管理,而非德州仪器 (TI)。

搜索工具按产品类型划分为以下类别:

  • 工具包括 IDE/编译器、调试和跟踪、仿真和建模软件以及闪存编程器。
  • 操作系统包括 TI 处理器支持的操作系统。
  • 应用软件是指应用特定的软件,包括在 TI 处理器上运行的中间件和库。
  • SoM 是模块上系统解决方案
封装 引脚 下载
NFBGA (ZCE) 361 查看选项
NFBGA (ZWT) 361 查看选项

订购和质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息:
  • 制造厂地点
  • 封装厂地点

推荐产品可能包含与 TI 此产品相关的参数、评估模块或参考设计。

支持和培训

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