UCC3583

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温度范围为 0°C 至 70°C 的开关模式次级侧后置稳压器

产品详情

Vin (max) (V) 15 Operating temperature range (°C) 0 to 70 Control mode Current Topology Boost, Flyback Rating Catalog Duty cycle (max) (%) 95
Vin (max) (V) 15 Operating temperature range (°C) 0 to 70 Control mode Current Topology Boost, Flyback Rating Catalog Duty cycle (max) (%) 95
SOIC (D) 14 51.9 mm² 8.65 x 6
  • Precision Secondary Side Post Regulation for Multiple Output Power Supplies
  • Useful for Both Single Ended and Center Tapped Secondary Circuits
  • Ideal Replacement for Complex Magnetic Amplifier Regulated Circuits
  • Leading Edge Modulation
  • Does Not Require Gate Drive Transformer
  • High Frequency (>500kHz) Operation
  • Applicable for Wide Range of Output Voltages
  • High Current Gate Driver (0.5A Sink/1.5A Source)
  • Average Current Limiting Loop

  • Precision Secondary Side Post Regulation for Multiple Output Power Supplies
  • Useful for Both Single Ended and Center Tapped Secondary Circuits
  • Ideal Replacement for Complex Magnetic Amplifier Regulated Circuits
  • Leading Edge Modulation
  • Does Not Require Gate Drive Transformer
  • High Frequency (>500kHz) Operation
  • Applicable for Wide Range of Output Voltages
  • High Current Gate Driver (0.5A Sink/1.5A Source)
  • Average Current Limiting Loop

The UCC3583 is a synchronizable secondary side post regulator for precision regulation of the auxiliary outputs of multiple output power supplies. It contains a leading edge pulse width modulator, which generates the gate drive signal for a FET power switch connected in series with the rectifying diode. The turn-on of the power switch is delayed from the leading edge of the secondary power pulse to regulate the output voltage. The UCC3583 contains a ramp generator slaved to the secondary power pulse, a voltage error amplifier, a current error amplifier, a PWM comparator and associated logic, a gate driver, a precision reference, and protection circuitry.

The ramp discharge and termination of the gate drive signal are triggered by the synchronization pulse, typically derived from the falling edge of the transformer secondary voltage. The ramp starts charging again once its low threshold is reached. The gate drive signal is turned on when the ramp voltage exceeds the control voltage. This leading edge modulation technique prevents instability when the UCC3583 is used in peak current mode primary controlled systems.

The controller operates from a floating power supply referenced to the output voltage being controlled. It features an undervoltage lockout (UVLO) circuit, a soft start circuit, and an averaging current limit amplifier. The current limit can be programmed to be proportional to the output voltage, thus achieving foldback operation to minimize the dissipation under short circuit conditions.

The UCC3583 is a synchronizable secondary side post regulator for precision regulation of the auxiliary outputs of multiple output power supplies. It contains a leading edge pulse width modulator, which generates the gate drive signal for a FET power switch connected in series with the rectifying diode. The turn-on of the power switch is delayed from the leading edge of the secondary power pulse to regulate the output voltage. The UCC3583 contains a ramp generator slaved to the secondary power pulse, a voltage error amplifier, a current error amplifier, a PWM comparator and associated logic, a gate driver, a precision reference, and protection circuitry.

The ramp discharge and termination of the gate drive signal are triggered by the synchronization pulse, typically derived from the falling edge of the transformer secondary voltage. The ramp starts charging again once its low threshold is reached. The gate drive signal is turned on when the ramp voltage exceeds the control voltage. This leading edge modulation technique prevents instability when the UCC3583 is used in peak current mode primary controlled systems.

The controller operates from a floating power supply referenced to the output voltage being controlled. It features an undervoltage lockout (UVLO) circuit, a soft start circuit, and an averaging current limit amplifier. The current limit can be programmed to be proportional to the output voltage, thus achieving foldback operation to minimize the dissipation under short circuit conditions.

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类型 标题 下载最新的英语版本 日期
* 数据表 Switch Mode Secondary Side Post Regulator 数据表 (Rev. B) 2005年 1月 18日
选择指南 电源管理指南 2018 (Rev. K) 2018年 7月 31日
选择指南 电源管理指南 2018 (Rev. R) 2018年 6月 25日
应用手册 适合高效、多输出应用的电源管理解决方案 2001年 10月 4日
应用手册 DN-83 UC3584DW Secondary Side Post Regulator EVM Board Schematic 1999年 9月 5日

设计和开发

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封装 引脚 下载
SOIC (D) 14 查看选项

订购和质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息:
  • 制造厂地点
  • 封装厂地点

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