ZHCSEQ1A February   2016  – February 2016 UCC28704

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Detailed Pin Description
        1. 7.3.1.1 VDD (Device Bias Voltage Supply)
        2. 7.3.1.2 GND (Ground)
        3. 7.3.1.3 VS (Voltage-Sense)
        4. 7.3.1.4 DRV (Gate Drive)
        5. 7.3.1.5 CS (Current Sense)
        6. 7.3.1.6 NTC/SU (NTC Thermistor Shutdown and External Start Up Control)
      2. 7.3.2 Primary-Side Regulation (PSR)
      3. 7.3.3 Primary-Side Constant Voltage (CV) Regulation
      4. 7.3.4 Primary-Side Constant Current (CC) Regulation
      5. 7.3.5 Valley-Switching and Valley-Skipping
      6. 7.3.6 Start-Up Operation
        1. 7.3.6.1 Initial Power-On with a Start-Up Resistor
        2. 7.3.6.2 Initial Power-On with A Depletion-Mode FET
      7. 7.3.7 Fault Protection
      8. 7.3.8 Constant Current Under-Voltage Protection
      9. 7.3.9 Load Transient Response
    4. 7.4 Device Functional Modes
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VDD Capacitance, CDD
        2. 8.2.2.2 VDD Start-Up Resistance, RSTR
        3. 8.2.2.3 Input Bulk Capacitance and Minimum Bulk Voltage
        4. 8.2.2.4 Transformer Turns Ratio, Inductance, Primary-Peak Current
        5. 8.2.2.5 Transformer Parameter Verification
        6. 8.2.2.6 VS Resistor Divider, Line Compensation, and NTC
        7. 8.2.2.7 Standby Power Estimate
        8. 8.2.2.8 Output Capacitance
        9. 8.2.2.9 Design Considerations in Using with Synchronous Rectifiers
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 器件命名规则
        1. 11.1.1.1  电容术语（以法拉为单位）
        2. 11.1.1.2  占空比术语
        3. 11.1.1.3  频率术语（以赫兹为单位）
        4. 11.1.1.4  电流术语（以安培为单位）
        5. 11.1.1.5  电流和电压调节术语
        6. 11.1.1.6  变压器术语
        7. 11.1.1.7  功率术语（以瓦特为单位）
        8. 11.1.1.8  电阻术语（以 Ω 为单位）
        9. 11.1.1.9  时序术语（以秒为单位）
        10. 11.1.1.10 电压术语（以伏特为单位）
        11. 11.1.1.11 交流电压术语（以 VRMS 为单位）
        12. 11.1.1.12 效率术语
    2. 11.2 文档支持
      1. 11.2.1 相关文档　
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VVDD Bias supply voltage 38 V
VS Voltage range –0.75 7 V
CS, NTC Voltage range –0.5 5 V
VDRV Gate-drive voltage at DRV –0.5 Self-limiting V
IDRV DRV continuous sink current 50 mA
IDRV DRV peak sourcing current, VDRV = 10 V to 0 V Self-limiting mA
IDRV DRV peak sink current, VDRV = 0 V to 10 V Self-limiting mA
IVS VS, peak, 1% duty-cycle, when detecting line voltage 1.2 mA
TJ Operating junction temperature range –55 150 °C
TSTG Storage temperature –65 150 °C
TLEAD Lead temperature 0.6 mm from case for 10 seconds 260 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
V(ESD) Electrostatic discharge Charged-device model (CDM) ESD stress voltage(2) ±500 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VDD Bias supply operating voltage 8.5 35 V
CDD VDD bypass capacitor 0.047 no limit µF
IVS VS pin sourcing current when detecting line voltage 1.0 mA
TJ Operating junction temperature –40 125 °C

6.4 Thermal Information

THERMAL METRIC UCC28704 UNIT
DBV
6 PINS
θJA Junction-to-ambient thermal resistance (1) 150 °C/W
θJCtop Junction-to-case (top) thermal resistance (2) 55 °C/W
θJB Junction-to-board thermal resistance (3) 60 °C/W
ψJT Junction-to-top characterization parameter (4) 3 °C/W
ψJB Junction-to-board characterization parameter (5) 55 °C/W
(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top.  No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.
(4) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(5) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).

6.5 Electrical Characteristics

Over operating free-air temperature range, VVDD = 25 V, RNTC = open, –40°C ≤ TA ≤ 125°C, TJ = TA (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BIAS SUPPLY INPUT
IRUN Supply current, run IDRV = 0, run state 1.65 2.3 2.65 mA
IWAIT Supply current, wait IDRV = 0, VVDD = 20 V, wait state 40 70 100 µA
ISTART Supply current, start IDRV = 0, VVDD = 17 V, start state 1.5 2.5 µA
IFAULT Supply current, fault IDRV = 0, fault state 1.7 2.2 2.8 mA
UNDER-VOLTAGE LOCKOUT
VVDD(on) VDD turn-on threshold VVDD low to high 17.5 21 23 V
VVDD(off) VDD turn-off threshold VVDD high to low 7.3 7.7 8.15 V
VS INPUT
VVSR Regulating level (1) Measured at no-load condition, TJ = 25°C 4.02 4.06 4.1 V
VVSNC Negative clamp level IVS = –300 µA 190 250 325 mV
IVSB Input bias current VVS = 4 V –0.25 0 0.25 µA
CS INPUT
VCST(max) Max CS threshold voltage (3) VVS = 3.70 V 720 750 784 mV
VCST(min) Min CS threshold voltage (3) VVS = 4.35 V 170 187.5 210 mV
KAM AM control ratio VCST(max) / VCST(min) 3.55 4 4.4 V/V
VCCR Constant-current regulating level 345 356 369 mV
KLC Line compensating current ratio, IVSLS /
(current out of CS pin)		 IVSLS = –300 µA 23 25 29 A/A
TCSLEB Leading-edge blanking time DRV output duration, VCS = 1 V 170 255 340 ns
DRV
IDRS DRV source current VDRV = 5 V, VVDD = 9 V 25 32 38 mA
RDRVLS DRV low-side drive resistance IDRV = 10 mA 6.5 12 Ω
VDRCL DRV clamp voltage VVDD = 35 V 9.5 10.6 13 V
RDRVSS DRV pull-down in start state 165 205 250 kΩ
TIMING
fSW(max) Maximum switching frequency (4) VVS = 3.7 V 78 85 94 kHz
fSW(min) Minimum switching frequency VVS = 4.6 V 0.88 1.03 1.18 kHz
tZTO Zero-crossing timeout delay 1.7 2.39 3 µs
tCCUV_BLANK Blanking delay time before CCUV shutdown VVS step from 3.5 V to 2.4 V to DRV stop switching 90 120 150 ms
PROTECTION
KOVP Over-voltage threshold ratio to VVSR VOVP/VVSR 1.13 1.15 1.18 V/V
VCCUV CCUV VO = 3.0 V TJ = 25℃, auto restart after fault 2.41 2.48 2.55 V
VOCP Over-current threshold At CS input 1.35 1.51 1.6 V
IVSL(run) VS line-sense run current Current out of VS pin – increasing 190 220 265 µA
IVSL(stop) VS line-sense stop current Current out of VS pin – decreasing 70 80 100 µA
KVSL VS line-sense ratio IVSL(run) / IVSL(stop) 2.55 2.8 2.95 A/A
TJ(stop) Thermal shut-down temperature (2) Internal junction temperature 150 °C
CABLE COMPENSATION
VCVS(max) Maximum compensation at VS Change in VS regulating level at full-load 180 220 260 mV
NTC INPUT
VNTCTH NTC shut-down threshold VDD UVLO cycle when below this threshold 0.9 0.95 1 V
INTC NTC pull-up current, out of pin VNTC = 1.1 V 90 100 120 µA
(1) The regulation level and OV threshold at VS decrease with increasing temperature by 1 mV/℃. This compensation over temperature is included to reduce the variances in power supply output regulation over-voltage detection with respect to the external output rectifier.
(2) Not tested in production.
(3) These threshold voltages represent average levels. This device automatically varies the current sense threshold to improve EMI performance.
(4) These frequency limits represent average levels. This device automatically varies the switching frequency to improve EMI performance.

6.6 Typical Characteristics

VDD = 25 V, unless otherwise noted.
UCC28704 D001_SLUSCA8.gif
Figure 1. Bias Supply Current vs. Bias Supply Voltage
UCC28704 D003_SLUSCA8.gif
Figure 3. VS Regulation Voltage vs. Temperature
UCC28704 D005_SLUSCA8.gif
Figure 5. Minimum CS Threshold Voltage vs. Temperature
UCC28704 D007_SLUSCA8.gif
Figure 7. Minimum Switching Frequency vs. Temperature
UCC28704 D009_SLUSCA8.gif
Figure 9. NTC Shutdown Threshold Voltage vs. Temperature
UCC28704 D011_SLUSCA8.gif
Figure 11. Constant-Current Under-Voltage Threshold vs. Temperature
UCC28704 D002_SLUSCA8.gif
Figure 2. Bias Supply Current vs. Temperature
UCC28704 D004_SLUSCA8.gif
Figure 4. Line-Sense Current vs. Temperature
UCC28704 D006_SLUSCA8.gif
Figure 6. Constant-Current Regulation Level vs. Temperature
UCC28704 D008_SLUSCA8.gif
Figure 8. DRV Source Current vs. Temperature
UCC28704 D010_SLUSCA8.gif
Figure 10. NTC Pullup Current vs. Temperature