ZHCSGN0A August   2017  – September 2017 TUSB214-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化电路原理图
      2.      显示屏
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 EQ
      2. 7.3.2 DC BOOST
      3. 7.3.3 BC1.2 CDP Support
    4. 7.4 Device Functional Modes
      1. 7.4.1 Low Speed (LS) Mode
      2. 7.4.2 Full Speed (FS) Mode
      3. 7.4.3 High Speed (HS) Mode
      4. 7.4.4 Shutdown Mode
      5. 7.4.5 I2C Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Test Procedure to Construct USB High Speed Eye Diagram
          1. 8.2.2.1.1 For a Host Side Application
          2. 8.2.2.1.2 For a Device Side Application
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.4.5 I2C Mode

TUSB214-Q1 supports 100 kHz I2C for device configuration, status readback and test purposes. This controller is enabled after SCL and SDA pins are sampled high shortly after de-assertion of RSTN. In this mode, the register as described in Table 2 can be accessed by I2C read/write transaction to 7-bit slave address 0x2C. It is necessary to set CFG_ACTIVE bit and reset it to zero after making changes to the EQ and DC Boost level registers to restart the state machine.

NOTE

All registers or fields in Table 2 which are not specifically mentioned are considered reserved. The default value of these reserved registers or fields must not be changed. It is suggested to perform a read-modify-write operation to maintain the default value of the reserved fields.

Table 2. Register definition

Offset Bit(s)NameTypeDefaultDescription
0x01 6:4 ACB_LVL RW XXX (Sampled from EQ pin at reset)

Sets the level of AC Boost

000 : Level 0 AC Boost programmed [MIN]

001 : Level 1 AC Boost programmed

011 : Level 2 AC Boost programmed

111 : Level 3 AC Boost programmed [MAX]
0x03 0 CFG_ACTIVE RW 1b

Configuration mode

0 : Normal mode. State machine enabled.

1 : Configuration mode: State machine disabled.

After reset, if I2C mode is true (SCL and SDA are both pulled high) it is maintained until it is cleared by an I2C write, but, if I2C mode is not true, it is cleared automatically.
0x0E 2:0 DCB_LVL RW XXX (Sampled from DC_BOOST pin at reset)

Sets the level of DC Boost

011 : 40mV (DC_Boost = L)

101 : 60mV (DC_Boost = M, default)

111 : 80mV (DC_Boost = H)