ZHCSGP0A July   2017  – September 2017 TPS7A39

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Startup Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Voltage Regulation
        1. 7.3.1.1 DC Regulation
        2. 7.3.1.2 AC and Transient Response
      2. 7.3.2 User-Settable Buffered Reference
      3. 7.3.3 Active Discharge
      4. 7.3.4 System Start-Up Controls
        1. 7.3.4.1 Start-Up Tracking
        2. 7.3.4.2 Sequencing
          1. 7.3.4.2.1 Enable (EN)
          2. 7.3.4.2.2 Undervoltage Lockout (UVLO) Control
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Setting the Output Voltages on Adjustable Devices
      2. 8.1.2  Capacitor Recommendations
      3. 8.1.3  Input and Output Capacitor (CINx and COUTx)
      4. 8.1.4  Feed-Forward Capacitor (CFFx)
      5. 8.1.5  Noise-Reduction and Soft-Start Capacitor (CNR/SS)
      6. 8.1.6  Buffered Reference Voltage
      7. 8.1.7  Overriding Internal Reference
      8. 8.1.8  Start-Up
        1. 8.1.8.1 Soft-Start Control (NR/SS)
          1. 8.1.8.1.1 In-Rush Current
        2. 8.1.8.2 Undervoltage Lockout (UVLOx) Control
      9. 8.1.9  AC and Transient Performance
        1. 8.1.9.1 Power-Supply Rejection Ratio (PSRR)
        2. 8.1.9.2 Channel-to-Channel Output Isolation and Crosstalk
        3. 8.1.9.3 Output Voltage Noise
        4. 8.1.9.4 Optimizing Noise and PSRR
        5. 8.1.9.5 Load Transient Response
      10. 8.1.10 DC Performance
        1. 8.1.10.1 Output Voltage Accuracy (VOUTx)
        2. 8.1.10.2 Dropout Voltage (VDO)
      11. 8.1.11 Reverse Current
      12. 8.1.12 Power Dissipation (PD)
        1. 8.1.12.1 Estimating Junction Temperature
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1: Single-Ended to Differential Isolated Supply
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Switcher Choice
          2. 8.2.1.2.2 Full Bridge Rectifier With Center-Tapped Transformer
          3. 8.2.1.2.3 Total Solution Efficiency
          4. 8.2.1.2.4 Feedback Resistor Selection
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Design 2: Getting the Full Range of a SAR ADC
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Detailed Design Description
          1. 8.2.2.3.1 Regulation of -0.2 V
          2. 8.2.2.3.2 Feedback Resistor Selection
        4. 8.2.2.4 Application Curves
  9. Power-Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
    2. 10.2 Layout Example
    3. 10.3 Package Mounting
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 开发支持
        1. 11.1.1.1 评估模块
        2. 11.1.1.2 Spice 模型
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Specifications

Absolute Maximum Ratings

over operating junction temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
Voltage INP –0.3 36 V
INN –36 0.3
OUTP –0.3 VINP + 0.3(5)
OUTN VINN – 0.3(4) 0.3
FBP –0.3 VINP + 0.3(7)
BUF –1 VINP + 0.3(7)
NR/SS –0.3 VINP + 0.3(8)
FBN VINN – 0.3(3) 0.3
EN –0.3 VINP + 0.3(6)
Current Output current Internally limited
Buffer current 2 mA
Temperature Operating junction temperature, TJ –55 150 °C
Storage, Tstg –65 150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages with respect to the ground pin, unless otherwise noted.
The absolute maximum rating is VINN – 0.3 V or –3 V, whichever is greater.
The absolute maximum rating is VINN – 0.3 V or –33 V, whichever is greater.
The absolute maximum rating is VINP + 0.3 V or 33 V, whichever is smaller.
The absolute maximum rating is VINP + 0.3 V or 36 V, whichever is smaller.
The absolute maximum rating is VINP + 0.3 V or 3 V, whichever is smaller.
The absolute maximum rating is VINP + 0.3 V or 2 V, whichever is smaller.

ESD Ratings

VALUE UNIT
VESD Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
|VINx| Supply voltage magnitude for either regulator 3.3 33 V
VEN Enable supply voltage 0 VINP V
VOUTP Positive regulated output voltage range VFBP 30 V
VOUTN Negative regulated output voltage range –30 VFBN V
IOUTx Output current for either regulator 0.005(2) 150 mA
IBUF Output current from the BUF pin 0 120 1000 µA
CINx Input capacitor for either regulator 4.7 10(1) µF
COUTx Output capacitor for either regulator 4.7 10(1) µF
CNR/SS Noise-reduction and soft-start capacitor 0(3) 10 1000 nF
CFFP Positive channel feed-forward capacitor; connect from VOUTP to FBP 0 10 100 nF
CFFN Negative channel feed-forward capacitor; connect from VOUTN to FBN 0 10 100 nF
R2P Lower positive feedback resistor 10 240
R2N Lower negative feedback resistor (from FBN to BUF) 10 240
TJ Operating junction temperature –40 125 °C
The nominal input and output capacitor value of 10-µF accounts for the derating factors that apply to X5R and X7R ceramic capacitors. The assumed overall derating is 80%.
Minimum load required when feedback resistors are not used. If feedback resistors are used, keeping R2x below 240 kΩ satisfies this requirement.
For startup tracking to function correctly a minimum 4.7-nF CNR/SS capacitor must be used.

Thermal Information

THERMAL METRIC(1) TPS7A39 UNIT
DSC (WSON)
10 PINS
RθJA Junction-to-ambient thermal resistance 44.4 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 33.7 °C/W
RθJB Junction-to-board thermal resistance 19.4 °C/W
ψJT Junction-to-top characterization parameter 0.4 °C/W
ψJB Junction-to-board characterization parameter 19.5 °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance 2.9 °C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

Electrical Characteristics

at TJ = –40°C to +125°C, VINP(nom) = VOUTP(nom) + 1 V or VIN(nom) = 3.3 V (whichever is greater), VINN(nom) = VOUTN(nom) – 1 V or VINN(nom) = –3.3 V (whichever is less), VEN = VINP, IOUT = 1 mA, CINx = 2.2 μF, COUTx = 10 μF, CFFx = CNR/SS = open, R1N = R2N = 10 kΩ, and FBP tied to OUTP (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VINP Input voltage range, positive channel 3.3 33 V
VINN Input voltage range, negative channel –33 –3.3 V
VUVLOP(rising) Undervoltage lockout threshold,
positive channel
VINP rising, VINN = –3.3 V 1.4 3.1 V
VUVLOP(hys) Undervoltage lockout threshold, positive channel hysteresis VINP falling, VINN = –3.3 V 120 mV
VUVLON(falling) Undervoltage lockout threshold,
negative channel
VINN falling, VINP = 3.3 V –3.1 –1.4 V
VUVLON(hys) Undervoltage lockout threshold, negative channel, hysteresis VINN rising, VINP = 3.3 V 70 mV
VNR/SS Internal reference voltage 1.172 1.19 1.208 V
VFBP Positive feedback voltage 1.170 1.188 1.206 V
VFBN Negative feedback voltage –10 3.7 10 mV
VOUT Output voltage range(2) Positive channel VFBP 30 V
Negative channel –30 VFBN(1)
VOUTP accuracy VINP(nom) ≤ VINP ≤ 33 V, 1 mA ≤ IOUTP ≤ 150 mA,
1.2 V ≤ VOUTP(nom) ≤ 30 V
–1.5 1.5 %VOUT
VOUTN accuracy(3) –33 V ≤ VINN ≤ VINN(nom), –150 mA ≤ IOUTN ≤ –1 mA, –30 V ≤ VOUTN(nom) ≤ –1.2 V –3 3 %VOUT
Negative VOUT channel accuracy –33 V ≤ VINN ≤ VINN(nom) , –150 mA ≤ IOUTN ≤ 1 mA, –1.2 V < VOUTN(nom) < 0 V –36 36 mV
–33 V ≤ VINN ≤ VINN(nom) , –150 mA ≤ IOUTN ≤ 1 mA, VOUTN(nom) = 0 V –12 12
ΔVOUT(ΔVIN) / VOUT(NOM) Line regulation, positive channel  VINP(nom) ≤ VINP ≤ 33 V 0.035 %VOUT
Line regulation, negative channel –33 V ≤ VINN ≤ VOUT(nom) + 1 V 0.125
ΔVOUT(ΔIOUT) / VOUT(NOM) Load regulation, positive channel  1 mA ≤ IOUTP ≤ 150 mA –0.09 %VOUT
Load regulation, negative channel –150 mA ≤ IOUTN ≤ –1 mA 0.715
VDO Dropout voltage Positive channel IOUTP = 50 mA, 3.3 V ≤ VINP(nom) ≤ 33.0 V,
VFBP = 1.070 V
175 300 mV
IOUTP = 150 mA, 3.3 V ≤ VINP(nom) ≤ 33.0 V,
VFBP = 1.070 V
300 500
Negative channel IOUTN = –50 mA, –3.3 V ≤ VINN(nom) ≤ –33.0 V,
VFBN = 0.0695 V
–250 –145
IOUTN = –150 mA, –3.3 V ≤ VINN(nom) ≤ –33.0 V,
VFBN = 0.0695 V
–400 –275
VBUF Buffered reference output voltage VNR/SS V
VBUF/IBUF Buffered reference load regulation IBUF = 100 µA to 1 mA 1 mV/mA
VBUF – VNR/SS Output buffer offset voltage VNR/SS = 0.25 V to 1.2 V –4 3 8 mV
VOUTP–VOUTN DC output voltage difference with a forced REF voltage VNR/SS = 0.25 V to 1.2 V –10 10 %VNR/SS
ILIM Current limit Positive channel VOUTP = 90% VOUTP(nom) 200 330 500 mA
Negative channel VOUTN = 90% VOUTN(nom) –500 –300 –200
ISUPPLY Supply current Positive channel IOUTP = 0 mA, R2N = open, VINP = 33 V 75 150 µA
IOUTP = 150 mA, R2N = open, VINP = 33 V 904
Negative channel IOUTN = 0 mA, VOUTN(nom)= 0 V, R2N = open, VINN = –33 V –150 –60
IOUTN = 150 mA, R2N = open, VINN = –33 V –1053
ISHDN Shutdown supply current Positive channel VEN = 0.4 V, VINP = 33 V 3.75 6.5 µA
Negative channel VEN = 0.4 V, VINN = –33 V –4.5 –2.25
IFBx Feedback pin leakage current Positive channel 5.5 100 nA
Negative channel –100 –9.7
INR/SS Soft-start charging current VNR/SS = 0.9 V 3 5.1 6.7 µA
IEN Enable pin leakage current VEN = VINP = 33 V 0.02 1 µA
VIH(EN) Enable high-level voltage 2.2 VINP V
VIL(EN) Enable low-level voltage 0 0.4 V
PSRR Power-supply rejection ratio |VIN| = 6 V, |VOUT(nom)| = 5 V, COUT = 10 μF, CNR/SS = CFF= 10 nF, f = 120 Hz 69 dB
Vn Output noise voltage Positive channel VINP = 3.3 V, VOUTP(nom) = VNR/SS, COUTP = 10 μF, CNR/SS = 10 nF, BW = 10 Hz to 100 kHz 20.63 µVRMS
VINP = 6 V, VOUTP(nom) = 5 V, COUTP = 10 μF, CNR/SS = CFF = 10 nF, BW = 10 Hz to 100 kHz 26.86
Negative channel VINN = –3 V, VOUTN(nom) = –VNR/SS, COUTP = 10 μF, CNR/SS = 10 nF, BW = 10 Hz to 100 kHz 22.13
VINN = –6 V, VOUTN(nom) = –5 V, COUTP = 10 μF, CNR/SS = CFF= 10 nF, BW = 10 Hz to 100 kHz 28.68
RNR/SS Filter resistor from band gap to NR pin 350
Tsd Thermal shutdown temperature Shutdown, temperature increasing 175 °C
Reset, temperature decreasing 160
VOUT(target) = 0 V, R1N = 10 kΩ, R2N = open.
To ensure VOUT does not drift up while the device is disabled, a minimum load current of 5 µA is required.
The device is not tested under conditions where the power dissipated across the device, PD, exceeds 2 W.

Startup Characteristics

at TJ = –40°C to +125°C, VINP(nom) = VOUTP(nom) + 1 V or VIN(nom) = 3.3 V (whichever is greater), VINN(nom) = VOUTN(nom) – 1 V or VINN(nom) = –3.3 V (whichever is less), VEN = VINP, IOUT = 1 mA, CINx = 2.2 μF, COUTx = 10 μF, CFFx = CNR/SS = 4.7nF, R1N = R2N = 10 kΩ, and FBP tied to OUTP (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tEN(delay) Delay time from EN low-to-high transition to 2.5% VOUTP From EN low-to-high transition to VOUTP = 2.5% × VOUTP(nom) 300 µs
tstart-up Delay time from EN low-to-high transition to both outputs reaching 95% of final value From EN low-to-high transition to VOUTP = VOUTP(nom) × 95% and VOUTN = VOUTN(nom) × 95% 1.1 ms
tPstart-Nstart Delay time from VOUTP leaving a high-impedance state to VOUTN leaving a high-impedance state From VOUTP = VOUTP(nom) × 2.5%  to VOUTN = VOUTN(nom) × 2.5% –40 –17 40 µs
Δ|VOUTP – VOUTN| Voltage difference between the positive and negative output During tPstart-Nstart 75 300 mV
TPS7A39 Timing_Diagram.gif

NOTE:

Slow ramps (trise(VINx) > 10 ms typically) on VINx with EN tied to VINP does not meet the tracking specification. Use a resistor divider from VINP to EN for these applications.
Figure 1. Start-Up Characteristics

Typical Characteristics

at TJ = 25°C, VINP = VOUTP(nom) + 1.0 V or VIN = 3.3 V (whichever is greater), VINN = VOUTN(nom) – 1 V or –3.3 V (whichever is less), VEN = VIN, IOUT = 1 mA, CIN = 10-μF ceramic, COUT = 10-μF ceramic, and CFFP = CFFN = CNR/SS = 10 nF (unless otherwise noted)
TPS7A39 tc_PSRR_vs_Vin_p5V_PosReg.gif
VOUTP = 5 V, IOUTP = 150 mA, VOUTN = –5 V, IOUTN = 0 mA, CNR/SS = CFFx = 10 nF
Figure 2. Positive PSRR vs Frequency and VINP
TPS7A39 tc_PSRR_vs_Iout_posReg_p5V.gif
VOUTP = 5 V, VINP = VEN = 6 V, VOUTN = –5 V, IOUTN = 0 mA, CNR/SS = CFFx = 10 nF
Figure 4. Positive PSRR vs Frequency and IOUTP
TPS7A39 tc_PSRR_vs_COUT_5Vout.gif
VOUTP = 5 V, VINP = VEN = 6 V, VOUTN = –5 V, IOUTN = 0 mA, CNR/SS = CFFx = 10 nF
Figure 6. Positive PSRR vs Frequency and COUTP
TPS7A39 tc_PSRR_vs_CFF_5Vout.gif
VOUTP = 5 V, VINP = VEN = 6 V, VOUTN = –5 V, IOUTN = 0 mA, CNR/SS = 10 nF
Figure 8. Positive PSRR vs Frequency and CFFP
TPS7A39 tc_PSRR_vs_CNR_5Vout.gif
VOUTP = 5 V, VINP = VEN = 6 V, VOUTN = –5 V, IOUTN = 0 mA,
CFFx = 10 nF
Figure 10. Positive PSRR vs Frequency and CNR/SS
TPS7A39 tc_CrossTalk_posToNeg.gif
Figure 12. Crosstalk Positive to Negative
TPS7A39 tc_Noise_vs_Vout_PosReg.gif
IOUTP = 150 mA, VINP = VEN, VOUTN = –VOUTP, IOUTN = 0 mA, CNR/SS = CFFx = 10 nF
Figure 14. Positive Spectral Noise Density vs Frequency and VOUTP
TPS7A39 tc_Noise_vs_Cnr_PosReg.gif
VOUTP = 5 V, IOUTP = 150 mA, VINP = VEN = 6 V, VOUTN = –5 V, IOUTN = 0 mA, CFFx = 10 nF
Figure 16. Positive Spectral Noise Density vs Frequency and CNR/SS
TPS7A39 tc_Noise_vs_Cff_PosReg.gif
VOUTP = 5 V, IOUTP = 150 mA, VINP = VEN = 6 V, VOUTN = –5 V, IOUTN = 0 mA, CNR/SS = 10 nF
Figure 18. Positive Spectral Noise Density vs Frequency and CFF
TPS7A39 tc_Noise_vs_Cout_PosReg.gif
VOUTP = 5 V, IOUTP = 150 mA, VINP = VEN = 6 V, VOUTN = –5 V, IOUTN = 0 mA, CNR/SS = CFFx = 10 nF
Figure 20. Positive Spectral Noise Density vs Frequency and COUT
TPS7A39 tc_Noise_vs_Iout_PosReg.gif
VOUTP = 5 V, VINP = VEN = 6 V, VOUTN = –5 V, IOUTN = 0 mA, CNR/SS = CFFx = 10 nF
Figure 22. Positive Spectral Noise Density vs Frequency and IOUT
TPS7A39 tc_vin_startup.gif
VOUTP = –VOUTN = 5 V, VINP = –VINN = 12 V
Figure 24. Startup (VINP = VEN)
TPS7A39 tc_PosReg_LineTransient_1VperUs.gif
VINP = 5.5 V to 10 V at 1 V/µs, VOUTP = –VOUTN = 5 V,
IOUTN = 0 mA, IOUTP = 150 mA
Figure 26. Line Transient Positive Regulator
TPS7A39 tc_PosReg_LineTransient_4VperUs.gif
VINP = 5.5 V to 10 V at 4 V/µs, VOUTP = –VOUTN = 5 V,
IOUTN = 0 mA, IOUTP = 150 mA
Figure 28. Line Transient Positive Regulator
TPS7A39 tc_PosReg_LoadTransient_1AperUs.gif
VINP = 6 V, VOUTP = –VOUTN = 5 V, IOUTN = 0 mA,
IOUTP = 1 mA to 150 mA at 1 A/µs
Figure 30. Load Transient Positive Regulator
TPS7A39 tc_lineregulation_0V.gif
VOUTN = 0 V
Figure 32. Negative Line Regulation
TPS7A39 tc_linereg_n1p2V_percent.gif
VOUTN = –1.19 V
Figure 34. Negative Line Regulation
TPS7A39 tc_linereg_n24V_percent.gif
VOUTN = –24 V
Figure 36. Negative Line Regulation
TPS7A39 tc_loadreg_n15V_percent.gif
VOUTN = –15 V, VINN = –16 V
Figure 38. Negative Load Regulation
TPS7A39 tc_loadreg_1p2V_percent.gif
VOUTP = 1.188 V, VINP = 3.3 V
Figure 40. Positive Load Regulation
TPS7A39 tc_loadreg_30V_percent.gif
VOUTP = 30 V, VINP = 33 V
Figure 42. Positive Load Regulation
TPS7A39 tc_linereg_15V_percent.gif
VOUTP = 15 V
Figure 44. Positive Line Regulation
TPS7A39 tc_currentLimit_pos1p2V.gif
VOUTP = 1.188 V
Figure 46. Positive Regulator Current Limit
TPS7A39 tc_dropout_150mA_posreg.gif
Figure 48. Positive Regulator Dropout Voltage vs
Input Voltage
TPS7A39 tc_dropout_vs_load_3p3V.gif
VINP = 3.3 V
Figure 50. Positive Regulator Dropout Voltage vs
Output Current
TPS7A39 tc_enable_threshold.gif
Figure 52. Enable Threshold vs Temperature
TPS7A39 tc_positive_activedischarge.gif
Figure 54. Positive Output Discharge Current vs
Output Voltage
TPS7A39 tc_SupplyCurrent_vs_outputCurrent_1p2V_PosReg.gif
VOUTP = 1.188 V
Figure 56. Positive Supply Current vs Output Current
TPS7A39 tc_Vbuf_vs_Iout_SBVS322.gif
VOUTN = –1.19 V
Figure 58. Buffer Accuracy vs Buffer Current
TPS7A39 tc_PSRR_vs_Vin_n5V_NegReg.gif
VOUTP = 5 V, IOUTP = 0 mA, VOUTN = –5 V, IOUTN = 150 mA, CNR/SS = CFFx = 10 nF
Figure 3. Negative PSRR vs Frequency and VINN
TPS7A39 tc_PSRR_vs_Iout_NegReg.gif
VOUTP = 5 V, IOUTP = 0 mA, VINN = –6 V, VOUTN = –5 V,
CNR/SS = CFFx = 10 nF
Figure 5. Negative PSRR vs Frequency and IOUTN
TPS7A39 tc_PSRR_vs_Cout_NegReg.gif
VOUTP = 5 V, IOUTP = 0 mA, VINN = –6 V, VOUTN = –5 V,
CNR/SS = CFFx = 10 nF, COUTP = 10 µF
Figure 7. Negative PSRR vs Frequency and COUTN
TPS7A39 tc_PSRR_vs_Cff_NegReg.gif
VOUTP = 5 V, IOUTP = 0 mA, VINN = –6 V, VOUTN = –5 V,
CNR/SS = CFFP = 10 nF
Figure 9. Negative PSRR vs Frequency and CFFN
TPS7A39 tc_PSRR_vs_Cnr_NegReg.gif
VOUTP = 5 V, IOUTP = 0 mA, VINN = –6 V, VOUTN = –5 V,
CFFx = 10 nF
Figure 11. Negative PSRR vs Frequency and CNR/SS
TPS7A39 tc_CrossTalk_negToPos.gif
Figure 13. Crosstalk Negative to Positive
TPS7A39 tc_Noise_vs_Vout_NegReg.gif
IOUTN = –150 mA, VINP = VEN, VOUTN = –VOUTP, IOUTP = 0 mA, CNR/SS = CFFx = 10 nF
Figure 15. Negative Spectral Noise Density vs Frequency and VOUTN
TPS7A39 tc_Noise_vs_Cnrss_NegReg.gif
VOUTN = –5 V, IOUTN = –150 mA, VINP = VEN = 6 V, VOUTN = –5 V, IOUTP = 0 mA, CFFx = 10 nF
Figure 17. Negative Spectral Noise Density vs Frequency and CNR/SS
TPS7A39 tc_Noise_vs_Cff_NegReg.gif
VOUTN = –5 V, IOUTN = –150 mA, VINP = VEN = 6 V, VOUTN = –5 V, IOUTP = 0 mA, CNR/SS = 10 nF
Figure 19. Negative Spectral Noise Density vs Frequency and CFF
TPS7A39 tc_Noise_vs_Cout_NegReg.gif
VOUTN = –5 V, IOUTN = –150 mA, VINP = VEN = 6 V, VOUTN = –5 V, IOUTP = 0 mA, CNR/SS = CFFx = 10 nF
Figure 21. Negative Spectral Noise Density vs Frequency and COUT
TPS7A39 tc_Noise_vs_Iout_NegReg.gif
VOUTN = –5 V, VINP = VEN = 6 V, VOUTN = –5 V, IOUTP = 0 mA, CNR/SS = CFFx = 10 nF
Figure 23. Negative Spectral Noise Density vs Frequency and IOUT
TPS7A39 tc_enable_startup.gif
VOUTP = –VOUTN = 5 V, VINP = –VINN = 15 V
Figure 25. Startup With EN
TPS7A39 tc_NegReg_LineTransient_1VperUs.gif
VINN = –5.5 V to –10 V at 1 V/µs, VOUTP = –VOUTN = 5 V,
IOUTN = –150 mA, IOUTP = 0 mA
Figure 27. Line Transient Negative Regulator
TPS7A39 tc_NegReg_LineTransient_4VperUs.gif
VINN = –5.5 V to –10 V at 4 V/µs, VOUTP = –VOUTN = 5 V,
IOUTN = –150 mA, IOUTP = 0 mA
Figure 29. Line Transient Negative Regulator
TPS7A39 tc_NegReg_LoadTransient_1AperUs.gif
VINN = –6 V, VOUTP = –VOUTN = 5 V, IOUTN = 0 mA,
IOUTN = –1 mA to –150 mA at 1 A/µs
Figure 31. Load Transient Negative Regulator
TPS7A39 tc_loadreg_0V_absolute.gif
VOUTN = 0 V, VINN = –3.3 V
Figure 33. Negative Load Regulation
TPS7A39 tc_linereg_n15V_percent.gif
VOUTN = –15 V
Figure 35. Negative Line Regulation
TPS7A39 tc_loadreg_n1p2V_percent.gif
VOUTN = –1.2 V, VINN = –3.3 V
Figure 37. Negative Load Regulation
TPS7A39 tc_loadreg_n30V_percent.gif
VOUTN = –30 V, VINN = –33 V
Figure 39. Negative Load Regulation
TPS7A39 tc_loadreg_15V_percent.gif
VOUTP = 15 V, VINP = 16 V
Figure 41. Positive Load Regulation
TPS7A39 tc_linereg_1p2V_percent.gif
VOUTP = 1.188 V
Figure 43. Positive Line Regulation
TPS7A39 tc_linereg_24V_percent.gif
VOUTP = 24 V
Figure 45. Positive Line Regulation
TPS7A39 tc_currentLimit_neg1p2V.gif
VOUTN = –1.19 V
Figure 47. Negative Regulator Current Limit
TPS7A39 tc_dropout_150mA_negreg.gif
Figure 49. Negative Regulator Dropout Voltage vs
Input Voltage
TPS7A39 tc_dropout_vs_load_n3p3V.gif
VOUTN = –3.3 V
Figure 51. Negative Regulator Dropout Voltage vs
Output Current
TPS7A39 tc_NR_current_vs_voltage.gif
Figure 53. INR/SS vs VNR/SS
TPS7A39 tc_negative_activedischarge.gif
Figure 55. Negative Output Discharge Current vs
Output Voltage
TPS7A39 tc_SupplyCurrent_vs_outputCurrent_n1p2V_NegReg.gif
VOUTN = –1.19 V
Figure 57. Negative Supply Current vs Output Current