ZHCSGZ6 October   2017 TPS6508700

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能框图
  2. 2修订历史记录
  3. 3Pin Configuration and Functions
    1. 3.1 Pin Functions
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Electrical Characteristics: Total Current Consumption
    6. 4.6  Electrical Characteristics: Reference and Monitoring System
    7. 4.7  Electrical Characteristics: Buck Controllers
    8. 4.8  Electrical Characteristics: Synchronous Buck Converters
    9. 4.9  Electrical Characteristics: LDOs
    10. 4.10 Electrical Characteristics: Load Switches
    11. 4.11 Digital Signals: I2C Interface
    12. 4.12 Digital Input Signals (CTLx)
    13. 4.13 Digital Output Signals (IRQB, GPOx)
    14. 4.14 Timing Requirements
    15. 4.15 Switching Characteristics
    16. 4.16 Typical Characteristics
  5. 5Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 SMPS Voltage Regulators
      1. 5.3.1 Controller Overview
      2. 5.3.2 Converter Overview
      3. 5.3.3 Dynamic Voltage Scaling
      4. 5.3.4 Current Limit
    4. 5.4 LDO Regulators and Load Switches
      1. 5.4.1 VTT LDO
      2. 5.4.2 LDOA1-LDOA3
      3. 5.4.3 Load Switches
    5. 5.5 Power Good Information (PGOOD or PG) and GPO Pins
    6. 5.6 Power Sequencing and Voltage-Rail Control
      1. 5.6.1 Power-Up and Power-Down Sequencing
      2. 5.6.2 Emergency Shutdown
    7. 5.7 Device Functional Modes
      1. 5.7.1 Off Mode
      2. 5.7.2 Standby Mode
      3. 5.7.3 Active Mode
    8. 5.8 I2C Interface
      1. 5.8.1 F/S-Mode Protocol
    9. 5.9 Register Maps
      1. 5.9.1  Register Map Summary
      2. 5.9.2  DEVICEID: PMIC Device and Revision ID Register (offset = 1h) [reset = 10h]
      3. 5.9.3  IRQ: PMIC Interrupt Register (offset = 2h) [reset = 0h]
      4. 5.9.4  IRQ_MASK: PMIC Interrupt Mask Register (offset = 3h) [reset = FFh]
      5. 5.9.5  PMICSTAT: PMIC Status Register (offset = 4h) [reset = 0h]
      6. 5.9.6  SHUTDNSRC: PMIC Shut-Down Event Register (offset = 5h) [reset = 0h]
      7. 5.9.7  BUCK2CTRL: BUCK2 Control Register (offset = 21h) [reset = 50h]
      8. 5.9.8  BUCK3DECAY: BUCK3 Decay Control Register (offset = 22h) [reset = 70h]
      9. 5.9.9  BUCK3VID: BUCK3 VID Register (offset = 23h) [reset = 70h]
      10. 5.9.10 BUCK3SLPCTRL: BUCK3 Sleep Control VID Register (offset = 24h) [reset = 70h]
      11. 5.9.11 BUCK4CTRL: BUCK4 Control Register (offset = 25h) [reset = Dh]
      12. 5.9.12 BUCK5CTRL: BUCK5 Control Register (offset = 26h) [reset = Dh]
      13. 5.9.13 BUCK6CTRL: BUCK6 Control Register (offset = 27h) [reset = Dh]
      14. 5.9.14 LDOA2CTRL: LDOA2 Control Register (offset = 28h) [reset = Ch]
      15. 5.9.15 LDOA3CTRL: LDOA3 Control Register (offset = 29h) [reset = 3Ch]
      16. 5.9.16 DISCHCTRL1: Discharge Control1 Register (offset = 40h) [reset = 55h]
      17. 5.9.17 DISCHCTRL2: Discharge Control2 Register (offset = 41h) [reset = 55h]
      18. 5.9.18 DISCHCTRL3: Discharge Control3 Register (offset = 42h) [reset = 15h]
      19. 5.9.19 PG_DELAY1: Power Good Delay1 Register (offset = 43h) [reset = 0h]
      20. 5.9.20 FORCESHUTDN: Force Emergency Shutdown Control Register (offset = 91h) [reset = 0h]
      21. 5.9.21 BUCK2SLPCTRL: BUCK2 Sleep Control Register (offset = 93h) [reset = 50h]
      22. 5.9.22 BUCK4VID: BUCK4 VID Register (offset = 94h) [reset = 20h]
      23. 5.9.23 BUCK4SLPVID: BUCK4 Sleep VID Register (offset = 95h) [reset = 20h]
      24. 5.9.24 BUCK5VID: BUCK5 VID Register (offset = 96h) [reset = 70h]
      25. 5.9.25 BUCK5SLPVID: BUCK5 Sleep VID Register (offset = 97h) [reset = E8h]
      26. 5.9.26 BUCK6VID: BUCK6 VID Register (offset = 98h) [reset = E8h]
      27. 5.9.27 BUCK6SLPVID: BUCK6 Sleep VID Register (offset = 99h) [reset = E8h]
      28. 5.9.28 LDOA2VID: LDOA2 VID Register (offset = 9Ah) [reset = FFh]
      29. 5.9.29 LDOA3VID: LDOA3 VID Register (offset = 9Bh) [reset = AAh]
      30. 5.9.30 BUCK123CTRL: BUCK1-3 Control Register (offset = 9Ch) [reset = 7h]
      31. 5.9.31 PG_DELAY2: Power Good Delay2 Register (offset = 9Dh) [reset = 21h]
      32. 5.9.32 SWVTT_DIS: SWVTT Disable Register (offset = 9Fh) [reset = 0h]
      33. 5.9.33 I2C_RAIL_EN1: VR Pin Enable Override1 Register (offset = A0h) [reset = 80h]
      34. 5.9.34 I2C_RAIL_EN2/GPOCTRL: VR Pin Enable Override2/GPO Control Register (offset = A1h) [reset = 89h]
      35. 5.9.35 PWR_FAULT_MASK1: VR Power Fault Mask1 Register (offset = A2h) [reset = C0h]
      36. 5.9.36 PWR_FAULT_MASK2: VR Power Fault Mask2 Register (offset = A3h) [reset = 3Fh]
      37. 5.9.37 GPO1PG_CTRL1: GPO1 PG Control1 Register (offset = A4h) [reset = C2h]
      38. 5.9.38 GPO1PG_CTRL2: GPO1 PG Control2 Register (offset = A5h) [reset = AFh]
      39. 5.9.39 GPO4PG_CTRL1: GPO4 PG Control1 Register (offset = A6h) [reset = 0h]
      40. 5.9.40 GPO4PG_CTRL2: GPO4 PG Control2 Register (offset = A7h) [reset = 0h]
      41. 5.9.41 GPO2PG_CTRL1: GPO2 PG Control1 Register (offset = A8h) [reset = C0h]
      42. 5.9.42 GPO2PG_CTRL2: GPO2 PG Control2 Register (offset = A9h) [reset = 2Fh]
      43. 5.9.43 GPO3PG_CTRL1: GPO3 PG Control1 Register (offset = AAh) [reset = 0h]
      44. 5.9.44 GPO3PG_CTRL2: GPO3 PG Control2 Register (offset = ABh) [reset = 0h]
      45. 5.9.45 MISCSYSPG Register (offset = ACh) [reset = FFh]
      46. 5.9.46 LDOA1CTRL: LDOA1 Control Register (offset = AEh) [reset = 7Dh]
      47. 5.9.47 PG_STATUS1: Power Good Status1 Register (offset = B0h) [reset = 0h]
      48. 5.9.48 PG_STATUS2: Power Good Status2 Register (offset = B1h) [reset = 0h]
      49. 5.9.49 PWR_FAULT_STATUS1: Power Fault Status1 Register (offset = B2h) [reset = 0h]
      50. 5.9.50 PWR_FAULT_STATUS2: Power Fault Status2 Register (offset = B3h) [reset = 0h]
      51. 5.9.51 TEMPCRIT: Temperature Fault Status Register (offset = B4h) [reset = 0h]
      52. 5.9.52 TEMPHOT: Temperature Hot Status Register (offset = B5h) [reset = 0h]
      53. 5.9.53 OC_STATUS: Overcurrent Fault Status Register (offset = B6h) [reset = 0h]
  6. 6Applications, Implementation, and Layout
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 Controller Design Procedure
          1. 6.2.2.1.1 Controller With External Feedback Resistor
          2. 6.2.2.1.2 Selecting the Inductor
          3. 6.2.2.1.3 Selecting the Output Capacitors
          4. 6.2.2.1.4 Selecting the FETs
          5. 6.2.2.1.5 Bootstrap Capacitor
          6. 6.2.2.1.6 Setting the Current Limit
          7. 6.2.2.1.7 Selecting the Input Capacitors
        2. 6.2.2.2 Converter Design Procedure
          1. 6.2.2.2.1 Selecting the Inductor
          2. 6.2.2.2.2 Selecting the Output Capacitors
          3. 6.2.2.2.3 Selecting the Input Capacitors
        3. 6.2.2.3 LDO Design Procedure
      3. 6.2.3 Application Curves
      4. 6.2.4 Layout
        1. 6.2.4.1 Layout Guidelines
        2. 6.2.4.2 Layout Example
    3. 6.3 Power Supply Coupling and Bulk Capacitors
    4. 6.4 Do's and Don'ts
  7. 7器件和文档支持
    1. 7.1 器件支持
      1. 7.1.1 第三方产品免责声明
    2. 7.2 文档支持
      1. 7.2.1 相关文档
    3. 7.3 接收文档更新通知
    4. 7.4 社区资源
    5. 7.5 商标
    6. 7.6 静电放电警告
    7. 7.7 术语表
  8. 8机械、封装和可订购信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • RSK|64
订购信息

器件概述

特性

  • 5.6V 至 21V 的宽输入电压范围
  • 三个可变输出电压同步
    降压控制器,采用 DCAP2™拓扑
    • 使用外部 FET 的可扩展输出电流,支持可选电流限制
    • 针对 BUCK2 和 BUCK6 进行 I2C 动态电压调节 (DVS) 控制,针对 BUCK1 进行外部反馈
  • 三个可变输出电压同步降压转换器,采用 DCS-Control 拓扑技术并支持 I2C DVS 功能
    • 输入电压 范围为 4.5V 至 5.5V
    • 输出电压范围为 0.425V 至 3.575V
    • 输出电流高达 3A
  • 三个具有可调节输出电压的 LDO 稳压器
    • LDOA1:可通过 I2C 选择的输出电压(1.35V 至 3.3V),输出电流高达 200mA
    • LDOA2 和 LDOA3:I2C 可选输出电压为 0.7V 至 1.5V,输出电流高达 600mA
  • 带有 BUCK6 的 LDO 作为输入电压
  • 三个具有压摆率控制功能的负载开关
    • 输出电流高达 300mA,压降小于标称输入电压的 1.5%
    • 输入电压为 1.8V 时,RDSON < 96mΩ
  • 5V 固定输出电压 LDO (LDO5)
    • 用于 SMPS 的栅极驱动器和 LDOA1 的电源
    • 可自动切换至 5V 降压以实现更高效率
  • 工厂 OTP 编程提供的内置时序功能
    • 用于 G3'、G3、S5 和 S0 状态选择的 CTL1、CTL4 和 CTL5
    • 用于 PG_S0 和 PG_S5 的 GPO1 和 GPO2
    • 漏极开路中断输出引脚
  • I2C 接口支持:
    • 标准模式(100kHz)
    • 快速模式(400kHz)
    • 快速模式+(1MHz)

应用

  • 2、3 或 4 电芯锂离子电池供电产品(NVDC 或非 NVDC)
  • 墙供电设计,特别是 12V 电源
  • 平板电脑、超极本和笔记本电脑
  • 移动 PC 和移动网络设备

说明

TPS6508700 器件是一款单芯片电源管理 IC (PMIC),专为笔记本电脑和一体式台式机的 AMD™系列 17h 型 10h-1Fh 处理器而设计。TPS6508700 器件可提供 5.6V 至 21V 的输入电压范围,用途 广泛。该器件非常适合使用 2S、3S 或 4S 锂离子电池组的 NVDC 和非 NVDC 电源架构。该 D-CAP2™和 DCS-Control™高频稳压器采用小型电感和电容,以减小解决方案体积。D-CAP2 和 DCS-Control 拓扑具有出色的瞬态响应性能,特别适用于具有快速负载开关的处理器内核和系统内存电压轨。I2C 接口可通过嵌入式控制器 (EC) 或片上系统 (SoC) 进行轻松控制。PMIC 采用带散热焊盘的 8mm × 8mm 单行 VQFN 封装,因此散热性能良好,电路板布线简单。

器件信息(1)

器件型号封装封装尺寸(标称值)
TPS6508700VQFN (64)8.00mm x 8.00mm
有关详细信息,请参阅 机械封装和可订购信息 部分。

功能框图

TPS6508700 BlockDiagram.gif
Figure 1-1 PMIC 功能框图