SLVSAN2D November   2010  – August 2016 TPS54328

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 PWM Operation
      2. 7.3.2 PWM Frequency and Adaptive On-Time Control
      3. 7.3.3 Auto-Skip Eco-Mode Control
      4. 7.3.4 Soft Start and Pre-Biased Soft Start
      5. 7.3.5 Current Protection
      6. 7.3.6 UVLO Protection
      7. 7.3.7 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Standby Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Voltage Resistors Selection
        2. 8.2.2.2 Output Filter Selection
        3. 8.2.2.3 Input Capacitor Selection
        4. 8.2.2.4 Bootstrap Capacitor Selection
        5. 8.2.2.5 VREG5 Capacitor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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10 Layout

10.1 Layout Guidelines

  • Keep the input switching current loop as small as possible.
  • Keep the SW node as physically small and short as possible to minimize parasitic capacitance and inductance and to minimize radiated emissions. Kelvin connections must be brought from the output to the feedback pin of the device.
  • Keep analog and non-switching components away from switching components.
  • Make a single point connection from the signal ground to power ground.
  • Do not allow switching current to flow under the device.
  • Keep the pattern lines for VIN and PGND broad.
  • Exposed pad of device must be connected to PGND with solder.
  • VREG5 capacitor must be placed near the device, and connected PGND.
  • Output capacitor must be connected to a broad pattern of the PGND.
  • Voltage feedback loop must be as short as possible, and preferably with ground shield.
  • Lower resistor of the voltage divider which is connected to the VFB pin must be tied to SGND.
  • Providing sufficient vias is preferable for VIN, SW and PGND connection.
  • PCB pattern for VIN, SW, and PGND must be as broad as possible.
  • VIN capacitor must be placed as near as possible to the device.

10.2 Layout Example

TPS54328 TPS54327_layout_a.gif Figure 16. PCB Layout
TPS54328 layout_DRC_lvsau1.gif Figure 17. PCB Layout for the DRC Package

10.3 Thermal Considerations

This 8-pin DDA package incorporates an exposed thermal pad that is designed to be directly to an external heat sink. The thermal pad must be soldered directly to the printed board (PCB). After soldering, the PCB can be used as a heat sink. In addition, through the use of thermal vias, the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a special heat sink structure designed into the PCB. This design optimizes the heat transfer from the integrated circuit (IC).

For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating abilities, see PowerPAD™ Thermally Enhanced Package and PowerPAD™ Made Easy.

The exposed thermal pad dimensions for this package are shown in Figure 18.

TPS54328 thermal pad.gif Figure 18. Thermal Pad Dimensions