SLUSCJ3A April  2016  – June 2016 TPS53632G

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1Absolute Maximum Ratings
    2. 6.2ESD Ratings
    3. 6.3Recommended Operating Conditions
    4. 6.4Thermal Information
    5. 6.5Electrical Characteristics
  7. Timing Requirements
  8. Switching Characteristics
  9. Typical Characteristics (Half-Bridge Operation)
  10. 10Detailed Description
    1. 10.1Overview
    2. 10.2Functional Block Diagram
    3. 10.3Feature Description
      1. 10.3.1 Current Sensing
      2. 10.3.2  Load Transients
      3. 10.3.3 PWM and SKIP Signals
      4. 10.3.4 5-V, 3.3-V and 1.8-V Undervoltage Lockout (UVLO)
      5. 10.3.5 Output Undervoltage Protection (UVP)
      6. 10.3.6 Overcurrent Protection (OCP)
      7. 10.3.7 Overvoltage Protection
      8. 10.3.8 Analog Current Monitor, IMON and Corresponding Digital Output Current
      9. 10.3.9 Addressing
      10. 10.3.10I2C Interface Operation
        1. 10.3.10.1Key for Protocol Examples
        2. 10.3.10.2Protocol Examples
      11. 10.3.11Start-Up Sequence
      12. 10.3.12Power Good Operation
      13. 10.3.13Fault Behavior
    4. 10.4Device Functional Modes
      1. 10.4.1 PWM Operation
    5. 10.5Configuration and Programming
      1. 10.5.1Operating Frequency
      2. 10.5.2Overcurrent Protection (OCP) Level
      3. 10.5.3IMON Gain
      4. 10.5.4Slew Rate
      5. 10.5.5Base Address
      6. 10.5.6Ramp Selection
      7. 10.5.7Active Phases
    6. 10.6Register Maps
      1. 10.6.1Voltage Select Register (VSR) (00h)
      2. 10.6.2IMON Register (03h)
      3. 10.6.3VMAX Register (04h)
      4. 10.6.4Power State Register (06h)
      5. 10.6.5SLEW Register (07h)
      6. 10.6.6Lot Code Registers (10-13h)
      7. 10.6.7Fault Register (14h)
  11. 11Applications and Implementation
    1. 11.1Application Information
    2. 11.2Typical Application
      1. 11.2.1D-CAP+™ Half-Bridge Application
        1. 11.2.1.1Design Requirements
        2. 11.2.1.2Detailed Design Procedure
          1. 11.2.1.2.1Step 1: Select Switching Frequency
          2. 11.2.1.2.2Step 2: Set The Slew Rate
          3. 11.2.1.2.3Step 3: Determine Inductor Value And Choose Inductor
          4. 11.2.1.2.4Step 4: Determine Current Sensing Method
          5. 11.2.1.2.5Step 5: DCR Current Sensing
          6. 11.2.1.2.6Step 6: Select OCP Level
          7. 11.2.1.2.7Step 7: Set the Load-Line Slope
          8. 11.2.1.2.8Step 8: Current Monitor (IMON) Setting
        3. 11.2.1.3Application Performance Plots
        4. 11.2.1.4Loop Compensation for Zero Load-Line
  12. 12Power Supply Recommendations
  13. 13 Layout
    1. 13.1Layout Guidelines
      1. 13.1.1PCB Layout
      2. 13.1.2Current Sensing Lines
      3. 13.1.3Feedback Voltage Sensing Lines
      4. 13.1.4PWM And SKIP Lines
        1. 13.1.4.1Minimize High Current Loops
      5. 13.1.5Power Chain Symmetry
      6. 13.1.6Component Location
      7. 13.1.7Grounding Recommendations
      8. 13.1.8Decoupling Recommendations
      9. 13.1.9Conductor Widths
    2. 13.2Layout Example
  14. 14Device and Documentation Support
    1. 14.1Trademarks
    2. 14.2Electrostatic Discharge Caution
    3. 14.3Glossary
  15. 15Mechanical, Packaging, and Orderable Information

1 Features

  • Valley Current Mode with Constant ON Time Control
  • Lossless Current Sensing Scheme
  • I2C Interface for VID Control and Telemetry
  • Programmable I2C Addresses up to Eight Devices
  • Switching Frequency up to 1 MHz
  • Digital Current Monitor
  • 7-Bit, DAC Output Range: 0.50-V to 1.52-V with 10-mV Step
  • Accurate, Adjustable Voltage Positioning or Zero Slope Load-Line
  • Selectable, 8-Level Current Limit
  • Adjustable Output Slew Rate Control
  • Default Boot Voltage: 1.00 V
  • Small, 4-mm × 4-mm, 32-Pin, VQFN, PowerPAD Package

2 Applications

  • 48-V Point-of-Load (POL) for Data Center and Telecommunication
  • Wide Input Range Power Supplies for Industrial

3 Description

The TPS53632G device is a half-bridge PWM controller with D-CAP+™ architecture that provides fast transient response, lowest output capacitance and high efficiency in single stage conversion directly from 48-V bus. The TPS53632G device supports the standard I2C Rev 3.0 interface for dynamic control of the output voltage and current monitor telemetry. Paired with TI GaN power stages and drivers, the TPS53632G can switch up to 1 MHz to minimize magnetic component size and reduce overall board space. The LMG5200 GaN power stage is designed specifically for this controller to achieve high frequency and efficiency as high as 92% with 48-V to 1-V conversion.

Other features include adjustable control of output slew rate and voltage positioning. In addition, the TPS53632G device can be used along with other TI discrete power MOSFETs and drivers for silicon-based half bridge solutions. The TPS53632G device is packaged in a space saving, thermally enhanced, 32-pin VQFN package and is rated to operate at a range between –10°C and 105°C.

Device Information

PART NUMBERPACKAGEBODY SIZE
TPS53632GVQFN4 mm × 4 mm

WHITESPACE

WHITESPACE

Simplified Schematic

TPS53632G simp_app_fp_sluscj3.gif