ZHCSGL1A May   2017  – May 2017 TPS2547

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Electrical Characteristics: High-Bandwidth Switch
    7. 6.7 Electrical Characteristics: Charging Controller
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Standard Downstream Port (SDP) USB 2.0/USB 3.0
      2. 8.3.2  Charging Downstream Port (CDP)
      3. 8.3.3  Dedicated Charging Port (DCP)
        1. 8.3.3.1 DCP BC1.2 and YD/T 1591-2009
        2. 8.3.3.2 DCP Divider Charging Scheme
        3. 8.3.3.3 DCP 1.2-V Charging Scheme
      4. 8.3.4  Wake on USB Feature (Mouse/Keyboard Wake Feature)
        1. 8.3.4.1 USB 2.0 Background Information
        2. 8.3.4.2 Wake On USB
        3. 8.3.4.3 USB Slow-Speed and Full-Speed Device Recognition
          1. 8.3.4.3.1 No CTL Pin Timing Requirement After Wake Event and Transition from S3 to S0
      5. 8.3.5  Load Detect
      6. 8.3.6  Power Wake
        1. 8.3.6.1 Implementing Power Wake in Notebook System
      7. 8.3.7  Port Power Management (PPM)
        1. 8.3.7.1 Benefits of PPM
        2. 8.3.7.2 PPM Details
        3. 8.3.7.3 Implementing PPM in a System with Two Charging Ports
      8. 8.3.8  Overcurrent Protection
      9. 8.3.9  FAULT Response
      10. 8.3.10 Undervoltage Lockout (UVLO)
      11. 8.3.11 Thermal Sense
    4. 8.4 Device Functional Modes
      1. 8.4.1 DCP Auto Mode
      2. 8.4.2 DCP Forced Shorted / DCP Forced Divider1
      3. 8.4.3 High-Bandwidth Data Line Switch
      4. 8.4.4 Device Truth Table (TT)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Output Discharge
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Current-Limit Settings
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

RTE Package
16-Pin WQFN
Top View

Pin Functions

PIN TYPE(1) DESCRIPTION
NO. NAME
1 IN P Input voltage and supply voltage; connect 0.1 μF or greater ceramic capacitor from IN to GND as close to the device as possible.
2 DM_OUT I/O D– data line to USB host controller.
3 DP_OUT I/O D+ data line to USB host controller.
4 ILIM_SEL I Logic-level input signal used to control the charging mode, current limit threshold, and load detection; see Table 3. Can be tied directly to IN or GND without pullup or pulldown resistor.
5 EN I Logic-level input for turning the power switch and the signal switches on/off; logic low turns off the signal and power switches and holds OUT in discharge. Can be tied directly to IN or GND without pullup or pulldown resistor.
6 CTL1 I Logic-level input used to control the charging mode and the signal switches; see Table 3. Can be tied directly to IN or GND without pullup or pulldown resistor.
7 CTL2 I Logic-level input used to control the charging mode and the signal switches; see Table 3. Can be tied directly to IN or GND without pullup or pulldown resistor.
8 CTL3 I Logic-level input used to control the charging mode and the signal switches; see Table 3. Can be tied directly to IN or GND without pullup or pulldown resistor.
9 STATUS O Active-low open-drain output, asserted in load detection conditions.
10 DP_IN I/O D+ data line to downstream connector.
11 DM_IN I/O D– data line to downstream connector.
12 OUT P Power-switch output.
13 FAULT O Active-low open-drain output, asserted during overtemperature or current limit conditions.
14 GND P Ground connection.
15 ILIM_LO I External resistor connection used to set the low current-limit threshold and the load detection current threshold. A resistor to ILIM_LO is optional; see Current-Limit Settings in Detailed Description.
16 ILIM_HI I External resistor connection used to set the high-current-limit threshold.
— Thermal Pad — Internally connected to GND; used to heatsink the part to the circuit board traces. Connect to GND plane.
(1) G = ground, I = input, O = output, P = power.