主页 电源管理 电源开关 电子保险丝和热插拔控制器

TPS2310

正在供货

具有非独立通道断路功能、使能端低电平有效的 3V 至 13V 双通道热插拔

产品详情

FET External Vin (min) (V) 3 Vin (max) (V) 13 Vabsmax_cont (V) 15 Current limit (min) (A) 0.01 Current limit (max) (A) 500 Overcurrent response Circuit breaker Fault response Latch-off Soft start Adjustable Features Fault output, Power good signal Rating Catalog Device type eFuses and hot swap controllers Operating temperature range (°C) -40 to 85 Function Inrush current control, Power good signal
FET External Vin (min) (V) 3 Vin (max) (V) 13 Vabsmax_cont (V) 15 Current limit (min) (A) 0.01 Current limit (max) (A) 500 Overcurrent response Circuit breaker Fault response Latch-off Soft start Adjustable Features Fault output, Power good signal Rating Catalog Device type eFuses and hot swap controllers Operating temperature range (°C) -40 to 85 Function Inrush current control, Power good signal
TSSOP (PW) 20 41.6 mm² 6.5 x 6.4
  • Dual-Channel High-Side MOSFET Drivers
  • IN1: 3 V to 13 V; IN2: 3 V to 5.5 V
  • Output dV/dt Control Limits Inrush Current
  • Circuit-Breaker With Programmable Overcurrent
    Threshold and Transient Timer
  • Power-Good Reporting With Transient Filter
  • CMOS- and TTL-Compatible Enable Input
  • Low, 5-µA Standby Supply Current .(Max)
  • Available in 20-Pin TSSOP Package
  • –40°C to 85°C Ambient Temperature Range
  • Electrostatic Discharge Protection
  • Dual-Channel High-Side MOSFET Drivers
  • IN1: 3 V to 13 V; IN2: 3 V to 5.5 V
  • Output dV/dt Control Limits Inrush Current
  • Circuit-Breaker With Programmable Overcurrent
    Threshold and Transient Timer
  • Power-Good Reporting With Transient Filter
  • CMOS- and TTL-Compatible Enable Input
  • Low, 5-µA Standby Supply Current .(Max)
  • Available in 20-Pin TSSOP Package
  • –40°C to 85°C Ambient Temperature Range
  • Electrostatic Discharge Protection

The TPS2310 and TPS2311 are dual-channel hot-swap controllers that use external N-channel MOSFETs as high-side switches in power applications. Features of these devices, such as overcurrent protection (OCP), inrush current control, output-power status reporting, and the ability to discriminate between load transients and faults, are critical requirements for hot-swap applications.

The TPS2310/11 devices incorporate undervoltage lockout (UVLO) and power-good (PG) reporting to ensure the device is off at start-up and confirm the status of the output voltage rails during operation. Each internal charge pump, capable of driving multiple MOSFETs, provides enough gate-drive voltage to fully enhance the N-channel MOSFETs. The charge pumps control both the rise times and fall times (dv/dt) of the MOSFETs, reducing power transients during power up/down. The circuit-breaker functionality combines the ability to sense overcurrent conditions with a timer function; this allows designs such as DSPs, that may have high peak currents during power-state transitions, to disregard transients for a programmable period.

DISCH1, DISCH2 – DISCH1 and DISCH2 should be connected to the sources of the external N-channel MOSFET transistors connected to GATE1 and GATE2, respectively. These pins discharge the loads when the MOSFET transistors are disabled. They also serve as reference-voltage connections for internal gate voltage-clamp circuitry.

ENABLE or ENABLE – ENABLE for TPS2310 is active-low. ENABLE for TPS2311 is active-high. When the controller is enabled, both GATE1 and GATE2 voltages will power up to turn on the external MOSFETs. When the ENABLE pin is pulled high for TPS2310 or the ENABLE pin is pulled low for TPS2311 for more than 50 µs, the gate of the MOSFET is discharged at a controlled rate by a current source, and a transistor is enabled to discharge the output bulk capacitance. In addition, the device turns on the internal regulator PREREG (see VREG) when enabled and shuts down PREREG when disabled so that total supply current is less than 5 µA.

FAULT  – FAULT is an open-drain overcurrent flag output. When an overcurrent condition in either channel is sustained long enough to charge TIMER to 0.5 V, both channels latch off and pull this pin low. In order to turn the device back on, either the enable pin has to be toggled or the input power has to be cycled.

GATE1, GATE2 – GATE1 and GATE2 connect to the gates of external N-channel MOSFET transistors. When the device is enabled, internal charge-pump circuitry pulls these pins up by sourcing approximately 15 µA to each. The turnon slew rates depend upon the capacitance present at the GATE1 and GATE2 terminals. If desired, the turnon slew rates can be further reduced by connecting capacitors between these pins and ground. These capacitors also reduce inrush current and protect the device from false overcurrent triggering during powerup. The charge-pump circuitry generates gate-to-source voltages of 9 V–12 V across the external MOSFET transistors.

IN1, IN2 –  IN1 and IN2 should be connected to the power sources driving the external N-channel MOSFET transistors connected to GATE1 and GATE2, respectively. The TPS2310/TPS2311 draws its operating current from IN1, and both channels remains disabled until the IN1 power supply has been established. The IN1 channel has been constructed to support 3-V, 5-V, or 12-V operation, while the IN2 channel has been constructed to support 3-V or 5-V operation

ISENSE1, ISENSE2, ISET1, ISET2 – ISENSE1 and ISENSE2, in combination with ISET1 and ISET2, implement overcurrent sensing for GATE1 and GATE2. ISET1 and ISET2 set the magnitude of the current that generates an overcurrent fault, through external resistors connected to ISET1 and ISET2. An internal current source draws 50 µA from ISET1 and ISET2. With a sense resistor from IN1 to ISENSE1 or from IN2 to ISENSE2, which is also connected to the drains of external MOSFETs, the voltage on the sense resistor reflects the load current. An overcurrent condition is assumed to exist if ISENSE1 is pulled below ISET1 or if ISENSE2 is pulled below ISET2. To ensure proper circuit breaker operation, VI(ISENSE1) and VI(ISET1) should never exceed VI(IN1). Similarly, VI(ISENSE2) and VI(ISET2) should never exceed VI(IN2).

PWRGD1, PWRGD2 – PWRGD1 and PWRGD2 signal the presence of undervoltage conditions on VSENSE1 and VSENSE2, respectively. These pins are open-drain outputs and are pulled low during an undervoltage condition. To minimize erroneous PWRGDx responses from transients on the voltage rail, the voltage sense circuit incorporates a 20-µs deglitch filter. When VSENSEx is lower than the reference voltage (about 1.23 V), PWRGDx is active low to indicate an undervoltage condition on the power-rail voltage. PWRGDx may not correctly report power conditions when the device is disabled, because there is no gate drive power for the PWRGD output transistor in the disable mode, or, in other words, PWRGD is floating. Therefore, PWRGD is pulled up to its pullup power supply rail in disable mode.

TIMER – A capacitor on TIMER sets the time during which the power switch can be in overcurrent before turning off. When the overcurrent protection circuits sense an excessive current, a current source is enabled which charges the capacitor on TIMER. Once the voltage on TIMER reaches approximately 0.5 V, the circuit-breaker latch is set and the power switch is latched off. Power must be recycled or the ENABLE pin must be toggled to restart the controller. In high-power or high-temperature applications, a minimum 50-pF capacitor is strongly recommended from TIMER to ground, to prevent any false triggering.

VREG – VREG is the output of an internal low-dropout voltage regulator, where IN1 is the input. The regulator is used to generate a regulated voltage source, less than 5.5 V, for the device. A 0.1-µF ceramic capacitor should be connected between VREG and ground to aid in noise rejection. In this configuration, upon disabling the device, the internal low-dropout regulator will also be disabled, which removes power from the internal circuitry and allows the device to be placed in low-quiescent-current mode. In applications where IN1 is less than 5.5 V, VREG and IN1 may be connected together. However, under these conditions, disabling the device does not place the device in low-quiescent-current mode, because the internal low-dropout voltage regulator is being bypassed, thereby keeping internal circuitry operational. If VREG and IN1 are connected together, a 0.1-µF ceramic capacitor between VREG and ground is not needed if IN1 already has a bypass capacitor of 1 µF to 10 µF.

VSENSE1, VSENSE2 – VSENSE1 and VSENSE2 can be used to detect undervoltage conditions on external circuitry. If VSENSE1 senses a voltage below approximately 1.23 V, PWRGD1 is pulled low. Similarly, a voltage less than 1.23 V on VSENSE2 causes PWRGD2 to be pulled low.

The TPS2310 and TPS2311 are dual-channel hot-swap controllers that use external N-channel MOSFETs as high-side switches in power applications. Features of these devices, such as overcurrent protection (OCP), inrush current control, output-power status reporting, and the ability to discriminate between load transients and faults, are critical requirements for hot-swap applications.

The TPS2310/11 devices incorporate undervoltage lockout (UVLO) and power-good (PG) reporting to ensure the device is off at start-up and confirm the status of the output voltage rails during operation. Each internal charge pump, capable of driving multiple MOSFETs, provides enough gate-drive voltage to fully enhance the N-channel MOSFETs. The charge pumps control both the rise times and fall times (dv/dt) of the MOSFETs, reducing power transients during power up/down. The circuit-breaker functionality combines the ability to sense overcurrent conditions with a timer function; this allows designs such as DSPs, that may have high peak currents during power-state transitions, to disregard transients for a programmable period.

DISCH1, DISCH2 – DISCH1 and DISCH2 should be connected to the sources of the external N-channel MOSFET transistors connected to GATE1 and GATE2, respectively. These pins discharge the loads when the MOSFET transistors are disabled. They also serve as reference-voltage connections for internal gate voltage-clamp circuitry.

ENABLE or ENABLE – ENABLE for TPS2310 is active-low. ENABLE for TPS2311 is active-high. When the controller is enabled, both GATE1 and GATE2 voltages will power up to turn on the external MOSFETs. When the ENABLE pin is pulled high for TPS2310 or the ENABLE pin is pulled low for TPS2311 for more than 50 µs, the gate of the MOSFET is discharged at a controlled rate by a current source, and a transistor is enabled to discharge the output bulk capacitance. In addition, the device turns on the internal regulator PREREG (see VREG) when enabled and shuts down PREREG when disabled so that total supply current is less than 5 µA.

FAULT  – FAULT is an open-drain overcurrent flag output. When an overcurrent condition in either channel is sustained long enough to charge TIMER to 0.5 V, both channels latch off and pull this pin low. In order to turn the device back on, either the enable pin has to be toggled or the input power has to be cycled.

GATE1, GATE2 – GATE1 and GATE2 connect to the gates of external N-channel MOSFET transistors. When the device is enabled, internal charge-pump circuitry pulls these pins up by sourcing approximately 15 µA to each. The turnon slew rates depend upon the capacitance present at the GATE1 and GATE2 terminals. If desired, the turnon slew rates can be further reduced by connecting capacitors between these pins and ground. These capacitors also reduce inrush current and protect the device from false overcurrent triggering during powerup. The charge-pump circuitry generates gate-to-source voltages of 9 V–12 V across the external MOSFET transistors.

IN1, IN2 –  IN1 and IN2 should be connected to the power sources driving the external N-channel MOSFET transistors connected to GATE1 and GATE2, respectively. The TPS2310/TPS2311 draws its operating current from IN1, and both channels remains disabled until the IN1 power supply has been established. The IN1 channel has been constructed to support 3-V, 5-V, or 12-V operation, while the IN2 channel has been constructed to support 3-V or 5-V operation

ISENSE1, ISENSE2, ISET1, ISET2 – ISENSE1 and ISENSE2, in combination with ISET1 and ISET2, implement overcurrent sensing for GATE1 and GATE2. ISET1 and ISET2 set the magnitude of the current that generates an overcurrent fault, through external resistors connected to ISET1 and ISET2. An internal current source draws 50 µA from ISET1 and ISET2. With a sense resistor from IN1 to ISENSE1 or from IN2 to ISENSE2, which is also connected to the drains of external MOSFETs, the voltage on the sense resistor reflects the load current. An overcurrent condition is assumed to exist if ISENSE1 is pulled below ISET1 or if ISENSE2 is pulled below ISET2. To ensure proper circuit breaker operation, VI(ISENSE1) and VI(ISET1) should never exceed VI(IN1). Similarly, VI(ISENSE2) and VI(ISET2) should never exceed VI(IN2).

PWRGD1, PWRGD2 – PWRGD1 and PWRGD2 signal the presence of undervoltage conditions on VSENSE1 and VSENSE2, respectively. These pins are open-drain outputs and are pulled low during an undervoltage condition. To minimize erroneous PWRGDx responses from transients on the voltage rail, the voltage sense circuit incorporates a 20-µs deglitch filter. When VSENSEx is lower than the reference voltage (about 1.23 V), PWRGDx is active low to indicate an undervoltage condition on the power-rail voltage. PWRGDx may not correctly report power conditions when the device is disabled, because there is no gate drive power for the PWRGD output transistor in the disable mode, or, in other words, PWRGD is floating. Therefore, PWRGD is pulled up to its pullup power supply rail in disable mode.

TIMER – A capacitor on TIMER sets the time during which the power switch can be in overcurrent before turning off. When the overcurrent protection circuits sense an excessive current, a current source is enabled which charges the capacitor on TIMER. Once the voltage on TIMER reaches approximately 0.5 V, the circuit-breaker latch is set and the power switch is latched off. Power must be recycled or the ENABLE pin must be toggled to restart the controller. In high-power or high-temperature applications, a minimum 50-pF capacitor is strongly recommended from TIMER to ground, to prevent any false triggering.

VREG – VREG is the output of an internal low-dropout voltage regulator, where IN1 is the input. The regulator is used to generate a regulated voltage source, less than 5.5 V, for the device. A 0.1-µF ceramic capacitor should be connected between VREG and ground to aid in noise rejection. In this configuration, upon disabling the device, the internal low-dropout regulator will also be disabled, which removes power from the internal circuitry and allows the device to be placed in low-quiescent-current mode. In applications where IN1 is less than 5.5 V, VREG and IN1 may be connected together. However, under these conditions, disabling the device does not place the device in low-quiescent-current mode, because the internal low-dropout voltage regulator is being bypassed, thereby keeping internal circuitry operational. If VREG and IN1 are connected together, a 0.1-µF ceramic capacitor between VREG and ground is not needed if IN1 already has a bypass capacitor of 1 µF to 10 µF.

VSENSE1, VSENSE2 – VSENSE1 and VSENSE2 can be used to detect undervoltage conditions on external circuitry. If VSENSE1 senses a voltage below approximately 1.23 V, PWRGD1 is pulled low. Similarly, a voltage less than 1.23 V on VSENSE2 causes PWRGD2 to be pulled low.

下载 观看带字幕的视频 视频

您可能感兴趣的相似产品

open-in-new 比较替代产品
功能与比较器件相似
TPS25985 正在供货 具有准确、快速电流监测器的 4.5V 至 16V、0.59mΩ、80A 可堆叠紧凑型电子保险丝 Single-channel eFuse with integrated MOSFET-capable of support 80A

技术文档

star =有关此产品的 TI 精选热门文档
未找到结果。请清除搜索并重试。
查看全部 5
类型 标题 下载最新的英语版本 日期
* 数据表 Dual Hot-Swap Controllers with Interdependent Circuit Breaker and Power-Good Rep 数据表 (Rev. H) 2013年 5月 10日
选择指南 电源管理指南 2018 (Rev. K) 2018年 7月 31日
选择指南 电源管理指南 2018 (Rev. R) 2018年 6月 25日
选择指南 Hot Swap Selection Tool 2015年 7月 28日
用户指南 Dual Hot Swap Controller Evaluation Module and Interface Card 2000年 4月 10日

设计和开发

如需其他信息或资源,请点击以下任一标题进入详情页面查看(如有)。

计算工具

TPS23XXCALC TPS230x/1x/2x/3x Design Calculator

This design utility allows the user to calculate the component values for external MOSFET, current limit setting, current limit sense resistor RSENSE, current limit setting resistor RSET, GATE capacitance Cg, TIMER capacitance CT, power-good feedback resistor divider, and other essential components (...)

支持的产品和硬件

支持的产品和硬件

产品
电子保险丝和热插拔控制器
TPS2300 具有独立通道断路功能、使能端低电平有效的 3V 至 13V 双通道热插拔 TPS2301 具有独立通道断路和电源正常指示功能的 3V 至 13V 双通道热插拔 TPS2310 具有非独立通道断路功能、使能端低电平有效的 3V 至 13V 双通道热插拔 TPS2311 具有非独立通道断路和电源正常指示功能的 3V 至 13V 双通道热插拔 TPS2320 使能端低电平有效的 3V 至 13V 双通道热插拔 TPS2321 使能端高电平有效的 3V 至 13V 双通道热插拔 TPS2330 使能端低电平有效的 3V 至 13V 热插拔控制器 TPS2331 使能端高电平有效的 3V 至 13V 热插拔控制器
计算工具

TVS-RECOMMENDATION-CALC TVS diode recommendation tool

This tool suggests suitable TVS for given system parameters and abs max voltage rating of the device.
支持的产品和硬件

支持的产品和硬件

此设计资源支持这些类别中的大部分产品。

查看产品详情页,验证是否能提供支持。

模拟工具

PSPICE-FOR-TI — 适用于 TI 设计和模拟工具的 PSpice®

PSpice® for TI 可提供帮助评估模拟电路功能的设计和仿真环境。此功能齐全的设计和仿真套件使用 Cadence® 的模拟分析引擎。PSpice for TI 可免费使用,包括业内超大的模型库之一,涵盖我们的模拟和电源产品系列以及精选的模拟行为模型。

借助 PSpice for TI 的设计和仿真环境及其内置的模型库,您可对复杂的混合信号设计进行仿真。创建完整的终端设备设计和原型解决方案,然后再进行布局和制造,可缩短产品上市时间并降低开发成本。

在 PSpice for TI 设计和仿真工具中,您可以搜索 TI (...)
封装 引脚 下载
TSSOP (PW) 20 查看选项

订购和质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息:
  • 制造厂地点
  • 封装厂地点

支持和培训

视频