ZHCSDT9C June 2015  – June 2015

PRODUCTION DATA. 

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Audio Characteristics (BTL)
    7. 7.7 Audio Characteristics (SE)
    8. 7.8 Audio Characteristics (PBTL)
    9. 7.9 Typical Characteristics, BTL Configuration
    10. 7.10Typical Characteristics, SE Configuration
    11. 7.11Typical Characteristics, PBTL Configuration
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1Overview
    2. 9.2Functional Block Diagrams
    3. 9.3Feature Description
      1. 9.3.1Error Reporting
    4. 9.4Device Protection System
      1. 9.4.1Overload and Short Circuit Current Protection
      2. 9.4.2DC Speaker Protection
      3. 9.4.3Pin-to-Pin Short Circuit Protection (PPSC)
      4. 9.4.4Overtemperature Protection OTW and OTE
      5. 9.4.5Undervoltage Protection (UVP) and Power-on Reset (POR)
      6. 9.4.6Fault Handling
      7. 9.4.7Device Reset
  10. 10Application and Implementation
    1. 10.1Application Information
    2. 10.2Typical Applications
      1. 10.2.1Stereo BTL Application
        1. 10.2.1.1Design Requirements
        2. 10.2.1.2Detailed Design Procedures
          1. 10.2.1.2.1Decoupling Capacitor Recommendations
          2. 10.2.1.2.2PVDD Capacitor Recommendation
          3. 10.2.1.2.3PCB Material Recommendation
          4. 10.2.1.2.4Oscillator
      2. 10.2.2Application Curves
      3. 10.2.3Typical Application, Single Ended (1N) SE
        1. 10.2.3.1Design Requirements
        2. 10.2.3.2Detailed Design Procedures
        3. 10.2.3.3Application Curves
      4. 10.2.4Typical Application, Differential (2N) PBTL
        1. 10.2.4.1Design Requirements
        2. 10.2.4.2Detailed Design Procedures
        3. 10.2.4.3Application Curves
  11. 11Power Supply Recommendations
    1. 11.1Power Supplies
      1. 11.1.1VDD Supply
    2. 11.2Powering Up
    3. 11.3Powering Down
  12. 12Layout
    1. 12.1Layout Guidelines
    2. 12.2Layout Examples
      1. 12.2.1BTL Application Printed Circuit Board Layout Example
      2. 12.2.2SE Application Printed Circuit Board Layout Example
      3. 12.2.3PBTL Application Printed Circuit Board Layout Example
  13. 13器件和文档支持
    1. 13.1文档支持
    2. 13.2社区资源
    3. 13.3商标
    4. 13.4静电放电警告
    5. 13.5Glossary
  14. 14机械、封装和可订购信息

6 Pin Configuration and Functions

The TPA3251D2 is available in a thermally enhanced TSSOP package.

The package type contains a heat slug that is located on the top side of the device for convenient thermal coupling to the heat sink.

DDV Package
HTSSOP 44-Pin
(Top View)
TPA3251D2 DDV-44.gif

Pin Functions

NAMENO.I/ODESCRIPTION
AVDD14PInternal voltage regulator, analog section
BST_A44PHS bootstrap supply (BST), external 0.033 μF capacitor to OUT_A required.
BST_B43PHS bootstrap supply (BST), external 0.033 μF capacitor to OUT_B required.
BST_C24PHS bootstrap supply (BST), external 0.033 μF capacitor to OUT_C required.
BST_D23PHS bootstrap supply (BST), external 0.033 μF capacitor to OUT_D required.
CLIP_OTW21OClipping warning and Over-temperature warning; open drain; active low
C_START15OStartup ramp, requires a charging capacitor to GND
DVDD11PInternal voltage regulator, digital section
FAULT19OShutdown signal, open drain; active low
FREQ_ADJ8OOscillator freqency programming pin
GND12, 13, 25, 26, 33, 34, 41, 42PGround
GVDD_AB1PGate-drive voltage supply; AB-side, requires 0.1 µF capacitor to GND
GVDD_CD22PGate-drive voltage supply; CD-side, requires 0.1 µF capacitor to GND
INPUT_A5IInput signal for half bridge A
INPUT_B6IInput signal for half bridge B
INPUT_C16IInput signal for half bridge C
INPUT_D17IInput signal for half bridge D
M13IMode selection 1 (LSB)
M24IMode selection 2 (MSB)
OC_ADJ7I/OOver-Current threshold programming pin
OSC_IOM9I/OOscillator synchronization interface
OSC_IOP10OOscillator synchronization interface
OUT_A39, 40OOutput, half bridge A
OUT_B35OOutput, half bridge B
OUT_C32OOutput, half bridge C
OUT_D27, 28OOutput, half bridge D
PVDD_AB36, 37, 38PPVDD supply for half-bridge A and B
PVDD_CD29, 30, 31PPVDD supply for half-bridge C and D
RESET18IDevice reset Input; active low
VDD2PPower supply for internal voltage regulator requires a 10-µF capacitor with a 0.1-µF capacitor to GND for decoupling.
VBG20PInternal voltage reference requires a 0.1-µF capacitor to GND for decoupling.
PowerPad™PGround, connect to grounded heat sink

Table 1. Mode Selection Pins

MODE PINSINPUT MODEOUTPUT CONFIGURATIONDESCRIPTION
M2M1
002N + 12 × BTLStereo BTL output configuration
012N/1N + 11 x BTL + 2 x SE2.1 BTL + SE mode
102N + 11 x PBTLParallelled BTL configuration. Connect INPUT_C and INPUT_D to GND.
111N +14 x SESingle ended output configuration